HW System/SoC Architect

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

The work

You will represent the Architecture function in Ambiq’s Singapore development office and serve as the primary architectural guide for the site’s engineering team.

Your focus is the SoC’s peripheral subsystems — audio, imaging and display, and high- and low-speed interfaces — architected for the power budgets of battery-powered wearables and IoT devices. On a sub-threshold SoC, external interfaces frequently dominate the power budget, so decisions that are routine elsewhere (when a link wakes, what stays retained, how data moves without waking the CPU) become first-order architectural problems.

These subsystems live on both sides of the package, and so does this role. Defining them properly requires fluency beyond the pins: cable and connector requirements, board-level electrical constraints, PHY behavior, and the driver model on the far side of the interface. A USB mode definition that ignores cable power delivery or the host driver stack is wrong before tape-out. You will be expected to reason across that whole span — and to deliver it as silicon architecture.

What you’ll own

Ordered by how you’ll spend your time — the silicon lifecycle runs through all of it.

Architecture specifications for the SoC’s peripheral subsystems: micro-architecture definition, flow and sequence diagrams, power and performance models, and pseudocode — the documents RTL design and verification teams implement from

Off-die interface definition — modes, electrical and protocol behavior, and integration requirements that account for boards, cables, connectors, PHYs, and the software driver model

Debug at RTL and gate level with the design team when implementation raises questions the specification must answer

Partnership with physical design to ensure robust, optimal implementation of what you specify

Power and performance trade-off analysis across full system dataflows — die, package, board, and software — guiding both hardware and software development

IP investigation, assessment, and selection — build-vs-license recommendations with the analysis to back them

Integration specifications covering system interfaces and external power management

Post-silicon analysis and support for delivery of SoC functionality into mass production

Use case and test case definition in support of validation

Who you’ll work with

RTL design and verification teams — the primary consumers of your specifications

Physical design — implementation feasibility, floorplan, and power-domain implications of architectural choices

The FPGA team — bringing up critical subsystem and interface features ahead of silicon

Software architecture — data and control flows, APIs, and hardware abstraction layers

Marketing, Advanced Development, and the Austin architecture team — technology roadmap and architectural alignment

Customers, applications engineering, and field teams — key features and competitive positioning

Required

Authorship of architectural specifications for SoCs, ASICs, or silicon IP — documents that hardware design teams implemented in RTL. This is the core of the role and the first thing we will ask about.

8+ years in SoC or ASIC architecture and design, or silicon IP development (hardware implemented in RTL — not firmware or driver development), targeting wearable, IoT, or mobile-class products

Experience architecting how an SoC connects to the external world — audio (I2S, PDM), imaging and display (MIPI CSI/DSI), and high- and low-speed links (USB, SPI, I2C)

Working knowledge of each interface on both sides of the package — board-level electrical constraints, cable and connector requirements (e.g., USB power delivery and cabling), PHY integration, and the operating-system driver model — sufficient to define modes and interfaces that hold up in real systems

Proven experience bringing low-power silicon architectures to market

Track record of taking novel solutions from concept through specification, design, and post-silicon validation

Working knowledge of low-power mobile consumer systems, and of embedded imaging or neural network processing

Strong systems-level thinking — able to reason across the hardware/software boundary and own trade-offs spanning multiple subsystems

Able to build consensus and drive architectural alignment across geographically distributed teams

Excellent written and verbal communication

BS in Electrical Engineering, Computer Engineering, or Computer Science

Preferred

MS or PhD in a related field

SoC fabric and interconnect technologies, power management architecture, UPF/power-aware design flows

Hands-on experience with advanced process nodes

Some team lead or management experience — this is an individual contributor role, but you will be the senior architectural voice on site

Location and eligibility

Based on-site in Singapore.