Senior Director, Silicon Architecture and Design Engineering (PCIe)

Job Details:

Job Description:

About the Role

Altera is seeking a Senior Director, Silicon Architecture and Design Engineering (PCIe) to lead our PCIe Center of Excellence and own the PCIe technology franchise across our programmable device portfolio, from multi-generation architecture and roadmap through hard and soft IP delivery, compliance, and customer enablement. The role is both the senior people leader for PCIe silicon engineering and Altera’s recognized technical authority on high-speed interconnect, setting technical direction, architecture, methodology, and roadmap for PCIe and adjacent coherent interconnect technologies.

The successful candidate brings deep experience leading large-scale silicon organizations and complex cross-functional silicon programs, together with multi-generation PCIe and high-speed I/O expertise supporting AI, cloud, networking, and edge applications.

Responsibilities:

Organizational Leadership

Lead, grow, and mentor a high-performing silicon engineering organization spanning design, SoC integration, and program execution, including hiring and developing engineering managers and senior technical leads.

Own delivery of complex FPGA, ASIC, and SoC products across the full silicon lifecycle: product definition, architecture, microarchitecture, RTL design, verification, DFT, emulation, implementation, bring-up, validation, and production ramp.

Drive scalable design methodologies, KPI-based execution frameworks, and automation that improve quality, predictability, and velocity, and shape long-range investment in the capabilities needed to scale Altera’s silicon roadmap.

Technical Leadership: PCIe Center of Excellence

Own PCIe technical direction end to end, covering protocol and controller architecture, PHY/SerDes integration, DMA, and virtualization across the PCIe stack.

Set architecture and integration strategy for PCIe and adjacent coherent interconnect such as CXL, aligned to emerging data-center and AI system architectures.

Lead PCIe subsystem decisions in high-performance SoCs, including IP reuse, controller/PHY integration, hard versus soft IP partitioning, and bandwidth, latency, reliability, and PPA tradeoffs. Direct hardware, firmware, and software co-design for feature enablement, error recovery, virtualization, and security.

Establish PCIe verification, validation, compliance, and interoperability strategy from pre-silicon verification and emulation through post-silicon bring-up and industry compliance.

Own the customer-facing PCIe deliverable end to end: hard IP and soft controller offerings, IP catalog and design-tool integration, reference designs, documentation, and design-in support.

Execution and Partnership

Drive execution of large, complex silicon programs, covering planning, prioritization, resource alignment, milestone tracking, and risk management against aggressive performance, quality, cost, and schedule targets, partnering across architecture, software, systems, product planning, physical design, product engineering, and manufacturing through bring-up and production ramp.

Represent silicon engineering in executive reviews, roadmap planning, and cross-functional leadership forums, communicating program status, key technical decisions, risks, mitigations, and resource needs.

Engage customers, ecosystem and IP/EDA/foundry partners, and standards organizations such as PCI-SIG and the CXL Consortium to shape Altera’s long-term interconnect roadmap.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$ 231,500 - $341,075 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 15+ years in silicon engineering, ASIC/SoC development, or FPGA product development.

10+ years of experience in PCIe and high-speed I/O technologies, including architecture, silicon development, or product development for compute, acceleration, storage, networking, or data-center infrastructure applications.

Deep expertise in PCIe architecture and protocol across the Transaction, Data Link, and Physical layers: link initialization and training, ordering, flow control, enumeration, power management, error handling, and PHY/SerDes integration.

Demonstrated experience architecting and integrating PCIe controller and PHY subsystems into complex SoCs, including endpoint and/or root-port architectures and host/device system integration.

Experience delivering PCIe Gen4 and/or Gen5 designs into production silicon, with working knowledge of the architectural changes introduced in subsequent generations.

Experience leading engineering managers and senior technical leads, and delivering PCIe features across the full silicon lifecycle through production ramp.

Preferred Qualifications

Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science; experience leading silicon development at advanced process nodes; and a track record of building and scaling silicon teams.

PCIe Gen6/Gen7 architectures: 64 and 128 GT/s signaling, PAM4, FLIT mode, forward error correction, L0p power management, advanced PHY/SerDes, link equalization and training, lane margining, bifurcation, and channel/package/board signal integrity including retimers.

Advanced PCIe capabilities such as SR-IOV, ATS, PASID, PRI, IOMMU integration, peer-to-peer, advanced error handling/RAS, and PCIe security.

CXL architecture and technologies, including CXL.io and, where applicable, CXL.cache, CXL.mem, coherency, memory expansion/pooling, or accelerator connectivity.

PCI-SIG compliance and interoperability: compliance workshops, Integrators List qualification, protocol and trace analysis, and interoperability across CPU, GPU, accelerator, NIC, SSD, switch, and retimer ecosystems.

FPGA architectures, programmable logic devices, or heterogeneous SoC platforms, including IP reuse across device families.

PCIe performance modeling, traffic analysis, QoS, and workload characterization for AI, HPC, cloud, storage, or accelerator platforms.

Adjacent interconnects such as UCIe or Ethernet; silicon security such as secure boot and hardware root of trust.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.