SoC verification

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a SoC verification based in United States.

This role offers the opportunity to take end-to-end ownership of verification for complex digital design blocks within advanced ASIC projects. You will build verification environments from the ground up using SystemVerilog and UVM, covering testbench infrastructure, sequences, agents, scoreboards, and functional coverage. The position combines hands-on verification execution with sophisticated debugging, regression management, and coverage closure. You will work on high-performance networking silicon and interconnect technologies, with exposure to protocols such as UCIe, PCIe, and Ethernet. Collaboration with engineering teams will be essential to align block-level verification with broader system-level infrastructure. The role suits an experienced verification engineer who can work independently while contributing effectively in a customer-facing environment.