Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a Senior Principal Product Engineer (8-12+ years industry experience) to lead advanced signoff methodology development, customer enablement, and product deployment activities for Cadence's timing signoff and ECO solutions. The ideal candidate will possess deep expertise in STA, MMMC signoff, ECO convergence, power optimization, signal integrity, and physical implementation, along with strong customer-facing skills and the ability to influence product direction through close collaboration with R&D and strategic semiconductor customers.

Key Responsibilities

• •Drive development and deployment of advanced signoff methodologies covering timing, power, signal integrity, and ECO closure.
• •Collaborate with customers, AE teams, and R&D to resolve complex design closure challenges.
• •Lead qualification and certification activities for advanced-node design flows.
• •Develop and optimize multi-mode multi-corner (MMMC) timing closure methodologies.
• •Drive signoff correlation across implementation, STA, SPICE, and signoff environments.
• •Define and validate methodologies for:
• •Setup and hold closure
• •Power optimization
• •Crosstalk mitigation
• •Glitch fixing
• •Max transition and electrical rule fixing
• •Multi-view timing closure

• •Support customer tapeouts and critical project milestones through root-cause analysis and debug.
• •Partner with R&D to prioritize and validate product enhancements and customer-driven requirements.
• •Create deployment collateral, technical presentations, and best-practice methodologies.
• •Drive adoption of emerging technologies including AI-assisted signoff and ECO automation.

Required Technical Skills

• •Strong expertise in Static Timing Analysis (STA)
• •Multi-mode multi-corner (MMMC) timing analysis
• •Signoff methodologies and timing convergence
• •Statistical timing analysis
• •Signal Integrity and Crosstalk Analysis
• •Glitch analysis and fixing methodologies
• •ECO implementation and closure flows
• •Timing correlation and SPICE correlation
• •Power optimization techniques
• •Boundary model and hierarchical timing flows
• •RC extraction and parasitic analysis
• •Physical implementation and signoff optimization

Desired Tool Experience

• •Cadence Tempus/PrimeTime
• •Cadence Innovus/ICC/FC
• •Tempus ECO/Tweaker
• •Physical implementation and signoff environments
• •AI-assisted design closure workflows

Preferred Industry Experience

• •Advanced-node ASIC or SoC development
• •Foundry qualification and certification programs
• •Customer-facing product engineering
• •Large-scale semiconductor design closure
• •Timing, power, and SI signoff methodologies

Leadership Expectations

• •Serve as technical lead for strategic customer engagements.
• •Influence product roadmap and methodology direction.
• •Mentor engineers and drive cross-functional collaboration.
• •Lead technical reviews and customer escalation management.

Required Experience

• •8-12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering.
• •Strong experience supporting advanced-node SoC/ASIC designs through implementation, timing closure, ECO convergence, and tapeout.
• •Proven experience working directly with semiconductor customers, R&D organizations, and field engineering teams to resolve complex technical challenges.
• •Hands-on experience developing and deploying production signoff methodologies across multiple technology nodes and large-scale designs.
• •Experience leading technical investigations, driving root-cause analysis, and influencing product enhancements for customer success.
• •Demonstrated ability to independently own strategic customer engagements and drive cross-functional execution.

Preferred Experience

• •Experience supporting advanced-node technologies (7nm, 5nm, 3nm, 2nm and beyond).
• •Experience with large SoC designs (>100M instance designs) and hierarchical signoff methodologies.
• •Experience with power-performance-area (PPA) optimization and signoff closure.
• •Experience with customer-facing technical leadership across strategic semiconductor accounts.
• •Experience in ECO closure methodologies, signal integrity analysis, glitch fixing, and timing correlation.
• •Exposure to AI-assisted implementation and signoff workflows is highly desirable.

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