hirly

UST

Senior FPGA Design Engineer

India

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hirly's read of this role

Seniority
Senior
Country
IN
Work mode
On-site / unstated
First seen by hirly
26 Sept 2026

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the posting

Position Overview: We are seeking a Senior FPGA Design Engineer specializing in porting, adapting, and optimizing complex IP cores to FPGA targets. In this role, the engineer will be responsible for the migration of ASIC RTL, System level models, or third-party IP into robust FPGA architectures, specifically managing high-speed protocol integration and advanced timing closure. The engineer will also be responsible for evaluating IP compatibility, rewriting or wrapper-engineering RTL to fit targ…

Original posting on UST's site ↗

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