ASIC / FPGA Digital Design Engineer – (Lead or Senior)

ASIC / FPGA Digital Design Engineer – (Lead or Senior)

Company:

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/ FPGA Digital Design Engineers – (Lead or Senior) to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products to support advanced digital subsystem development in an aerospace environment in El Segundo or Huntington Beach, CA.

Engineers may support ASIC, FPGA, or mixed ASIC/FPGA developments depending on program assignment, technical specialization, and organizational needs. Work may include requirements development and capture, architecture support, HDL development, simulation, synthesis, FPGA implementation, timing analysis, integration, troubleshooting, verification collaboration, and traceability activities depending on role level and assignment scope.

• Programs, Products, & Growth Opportunities
• Engineers contribute to advanced aerospace and defense programs spanning space, aviation, communications, and autonomous systems. Programs may include next-generation satellite and space systems, modules supporting NASA missions, Space Launch System (SLS)-related technologies, commercial and military aircraft platforms, autonomous aviation technologies, and emerging digital architectures supporting future aerospace systems.

Engineers support a broad portfolio spanning ASICs, SoCs, and FPGAs across multiple concurrent aerospace and defense programs. Collaborations within the broader organization include space and satellite efforts, commercial and military aviation programs, and autonomous aviation initiatives involving organizations such as Millennium Space Systems and Wisk Aero.

Department expertise spans requirements development, architecture activities, RTL design, ASIC development, FPGA implementation, timing analysis, verification collaboration, integration support, and system-level troubleshooting.

Engineers have opportunities to broaden across conceptual architecture, requirements development, HDL ownership, FPGA implementation, timing analysis, verification collaboration, subsystem development, and integration activities while deepening selected technical specialties over time. The organization intentionally supports growth from focused contributors toward broader technical ownership, subsystem responsibilities, mentorship, and technical leadership roles as experience develops.

Teams are intentionally composed of engineers with complementary strengths spanning architecture, implementation, verification, integration, timing, and troubleshooting. The role is not intended to imply that every engineer must simultaneously be an expert in all disciplines.

• Responsibilities
• •Support ASIC, FPGA, or mixed ASIC/FPGA developments depending on assignment
• •Contribute to requirements development, refinement, interface definition, conceptual architecture activities, and traceability efforts appropriate to role level
• •Develop HDL / RTL for ASIC, FPGA, and SoC systems
• •Compile, simulate, debug, and troubleshoot digital designs
• •Perform and/or support synthesis, implementation, constraints development, timing closure, and tool execution activities
• •Collaborate with verification teams to support simulation, debug, coverage, and integration goals
• •Apply timing concepts, CDC fundamentals, and integration considerations
• •Support broader system troubleshooting and integration activities
• •Communicate technical status, risks, dependencies, and tradeoffs proactively

• Behavioral Expectations
• •Operate with ownership appropriate to role level
• •Independently manage assigned scope and execution
• •Develop technical breadth while deepening selected expertise
• •Support peer development and technical collaboration
• •Build systems awareness beyond immediate design boundaries
• •Contribute to technical leadership activities appropriate to level

• Lead, Level 4
• •Support subsystem ownership activities
• •Mentor others
• •Lead larger technical efforts, integration activities, or technical teams

• Senior, Level 5
• •Provide technical leadership
• •Support architecture direction and broader technical ownership
• •Lead teams, subsystem efforts, and cross-functional initiatives

This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed locationa.

Basic Qualifications (Required Skills/Experience):

This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.

Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement

Bachelor’s degree and 9+ years of experience with years FPGA, ASIC, or SoC digital design; or a BS/MS and 7+ years of FPGA, ASIC, or SoC digital design experience

Experience with HDL development, simulation, debug, and synthesis

Strong digital design fundamentals (projects with digital logic design, computer architecture, etc)

Experience troubleshooting digital systems (debugging RTL design, HDL/architecture)

Understanding of timing fundamentals and CDC concepts

Preferred Qualifications (Desired Skills/Experience):

Senior, Level 5 : 14+ years of related engineering experience

Bachelor’s Degree or Master's Degree in EE, Computer Engineering/Science, or related field

Requirements development and traceability experience

FPGA implementation including constraints and timing closure

Static timing analysis experience

Verification collaboration experience

High-speed interfaces, processor integration, memory subsystems, or SoC integration

Mentoring or technical leadership exposure

Familiarity with industry-standard tools and methodologies

Conflict of Interest:

Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.

Typical Education/Experience:

Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Senior (Level 5): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation:

This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace:

Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies .

Shift Work:

This position is for 1st shift.

Total Rewards:

At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to