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NXP

ASIC Physical Verification Lead

Pune

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hirly's read of this role

Seniority
Lead / management
Country
IN
Work mode
On-site / unstated
First seen by hirly
27 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

We are looking for an experienced ASIC Physical Verification Lead with around 10 years of experience to drive physical verification signoff activities for complex SoC and IP designs across multiple technology nodes.

Key Responsibilities

  • Lead physical verification signoff for ASIC/SoC projects from block level to full-chip tapeout.
  • Own and drive closure of DRC, LVS, ERC, Antenna, Density, and reliability verification checks.
  • Debug complex physical verification issues and collaborate with Physical Design, Layout, Circuit Design, and Foundry teams for resolution.
  • Develop and enhance verification methodologies, automation, and signoff flows.
  • Mentor junior engineers and lead technical reviews.

Required Skills & Experience

  • 8-12 years of hands-on experience in ASIC Physical Verification.
  • Strong expertise in Calibre DRC/LVS/ERC/PERC and physical signoff methodologies.
  • Experience across multiple technology nodes, including 28nm and 16/14/12nm FinFET technologies .
  • Good understanding of semiconductor manufacturing rules, reliability checks, and tapeout requirements.
  • Proficiency in Tcl, Python, Perl, or Shell scripting .
  • Exposure to leading foundries such as TSMC, Samsung, or GlobalFoundries .
  • Strong problem-solving, debugging, and leadership skills.

Preferred

  • Experience with full-chip hierarchical verification.
  • Exposure to Analog/Mixed-Signal, Memory, or High-Speed Interface IPs.
  • Prior experience leading small teams and driving successful tapeouts.
  • Role: ASIC Physical Verification Lead
  • Experience: 8-12 Years
  • Domain: Semiconductor / ASIC / SoC Design Signoff
  • Location: Pune

More information about NXP in India...

#LI-9415

Original posting on NXP's site ↗

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