Digital ASIC Design / Verification Engineering Intern/Co-Op

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking an exceptional intern/co-op to join our Interface IP team in Toronto, Ontario!

Our Approach to Internships:

Make you an integral part of the team by providing training, mentorship, and encouraging your creative talents! As part of a smaller, tight-knit design group, you will be given opportunities to work on various tasks that span the entire business-engineering cycle. Our goal is to equip students with practical work experience and a big picture view of how business is conducted in the semiconductor industry. You will only be limited by your desire to learn and ambition to assume more responsibilities. We understand that it is best to learn by doing. We will provide tasks that enable you to learn while also making meaningful technical contributions. We also consider interns as full-fledged team members and as your knowledge grows, so does the number of tasks and their complexities. The internship program is also an important step in our full-time post-graduation recruitment strategy, with many of our former interns returning as full-time employees.

• Description:
• The Digital ASIC Design / Verification Engineering Intern will be reporting to digital engineering director and is a Full-Time position. The team is working on the next generation PCIe SERDES Phy IP. The Intern will work with cutting edge technology and EDA tools to develop and validate Cadence’ designs pre silicon. The intern is expected to interact extensively with logic, verification, physical design, analog and system engineers in the team. By the end of internship, the intern will have full exposure to all aspects of digital ASIC development from RTL design & verification to tape-out.

Responsibilities:

• •RTL coding, simulation, and verification
• •Design and verification flow automation, improvements, and development
• •Compiling timing constraints and performing logic synthesis
• •Interface with application engineering team on design integration issues and technical customer support requests
• •Collaborating with experienced engineers on managing multiple projects, build flows, and design/verification environments.

Skills/Requirements:

• •Students who have completed third year engineering in Electrical, Computer Engineering, or Engineering Science
• •Strong academic background, excellent verbal and written communication skills, and an ability to excel working in a team environment.
• •The successful candidate will be a proven self-starter with the ability to proactively identify problem situations and propose technically viable solutions.
• •Preferred candidate has experience in Verilog HDL and scripting with Python, Perl, or similar object-oriented languages.

Application Requirements:

Please include a resume and transcript with your application. Only complete applications will be reviewed.

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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.