Advantech
EE 硬體研發工程師 - Server (ACG/ 林口園區)
Linkou
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hirly's read of this role
- Seniority
- Mid level
- Country
- TW
- Work mode
- On-site / unstated
- First seen by hirly
- 27 Sept 2026
Derived automatically from the posting. Upload your resume above to see how the role scores against it.
the posting
- Responsibility:
- 1. Server 系統硬體設計(Intel Xeon / AMD EPYC x86 平台為主)，涵蓋 schematic design 與 high-speed layout review。
- 2. PCIe Gen5/Gen6、DDR5、SerDes 之 routing、stack-up / impedance control 設計。
- 3. Power sequencing 設計與驗證。
- 4. Platform bring-up and debug。
- 5. 與 BMC / CPLD、BIOS / firmware team 共同開發並負責量測驗證、問題協調及解決。
- 6. ODM 硬體及系統專案:負責 EVT / DVT / PVT 各階段之設計與驗證以及量產品(MP)的維護工作。
- Qualification:
- 1. 具 Server / x86 系統硬體設計經驗。
- 2. 大學以上電子 / 電機相關系所畢。
- 3. 熟悉 EDA 工具如OrCAD、Allegro，能進行 schematic 設計與 high-speed layout。
- 4. 熟悉 Intel / AMD 平台 design guide(EDS / PDG)及 DDR / PCIe routing rules，能據以進行 schematic / layout review。
- 5. 熟悉量測儀器high-bandwidth oscilloscope、logic / protocol analyzer 等。
- 6. 熟悉管理sideband 介面 I2C / I3C、SMBus、eSPI / LPC、SPI、JTAG、SGPIO、LTPI 等。
- 7. 熟悉伺服器產品架構，具 BIOS / POST debug、BMC console 操作能力。
A plus:
1. 了解 BMC(OpenBMC / AMI)、CPLD 基本架構佳。
2. 熟悉 Linux 環境操作佳。
- 3. 具 OCP 標準經驗者佳 DC-MHS / DC-SCM、OCP NIC 3.0、M-PIC、M-XIO、M-PESTI。
- 4. 具電子 / 電腦相關證照佳。
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