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Ricursive Intelligence

RTL and Design Verification Engineer

Palo Alto

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hirly's read of this role

Seniority
Mid level
Country
US
Work mode
On-site / unstated
First seen by hirly
28 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Ricursive Intelligence is a frontier AI lab building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. Backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures, we are a growing, fast-paced team where every hire shapes the work.

The company has unmatched talent density, including IMO, IPHO, and IOAA gold medalists, pioneers who made prior breakthroughs in chip design: AlphaChip (Nature 2021), ePlace (DAC Best Paper Nominee 2014), RL-CCD (DAC Best Paper 2023), INSTA (DAC Best Paper 2025), and C3PO (ASP-DAC Best Paper 2026), chip leads for Apple Silicon (multiple generations of iPhone and iPad) and Google (TPU, OpenTitan), and top researchers and engineers from Anthropic, Google DeepMind, Stanford, and MIT.

We are hiring best-in-class engineers and researchers with real depth in RTL and design verification. You will tackle deeply technical, high-impact challenges alongside an elite team that has previously shipped frontier AI models and advanced chips. As a startup, everyone is hands-on; you will design algorithms, run large-scale experiments, and ship products that transform chip design.

Original posting on Ricursive Intelligence's site ↗

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RTL and Design Verification Engineer · Palo Alto | hirly.me