Senior DFT (Design for test) Engineer

Job Description

• Are you in search for a new challenge? Are you equipped with forward looking
• spirit and experienced in digital design flows and tools? Design-for-Test (DFT) is
• a multi-disciplinary field of growing complexity which involves cooperation
• among multiple VLSI engineering skills, including design, architecture,
• verification, backend, timing, test, ATE and reliability and more.
• Take the opportunity and join us as a Senior DFT Engineer:

Your role

• DFT implementation inline with existing test methodology for advance process
• nodes
• • Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG,
• patterns validation/simulation, MBIST/LBIST
• • Closely work with physical design team to resolve timing constraints/issues
• • Verify DFT circuitry and interface with other components/IPs and debug timing
• simulation issues
• • Debug and improve important DfT KPIs: test coverage/pattern efficiency
• • Hierarchical retargeting
• • Silicon bring-up, diagnosis and support for physical failure analysis

Desired qualifications/skills:

• 6+ years of hands-on experience with DFT and test flows with commercial EDA tools
• for large and complex SOCs
• • Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield
• learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST
• • Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax,
• VCS, Tessent and Modus/Encounter tool suite
• • Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT,
• quality metrics is a plus
• • Hands-on in Perl/Tcl/Python scripting
• • Excellent analytical, and problem-solving skills

We offer you:

• •Competitive Salary & Benefits;
• •Respect for your private life and your choices;
• •All tools required for high performance in your field;
• •Responsible approach, long-term commitments, and stability.