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Senior Engineer (Level 2)
Bangalore, Karnataka, India
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hirly's read of this role
- Seniority
- Senior
- Country
- IN
- Work mode
- On-site / unstated
- First seen by hirly
- 27 Sept 2026
Derived automatically from the posting. Upload your resume above to see how the role scores against it.
the posting
Position: Senior Engineer (Level 2) Job Description: Roles and Responsibilities: · 4 years of experience in SOC/IP/block level functional verification using System Verilog/UVM. · Strong knowledge of UVM, advance UVM,System Verilog . · Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM. Understanding of complete functional verification cycle will be added advantage · Knowledge of at least one industry standard protocol…
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