hirly

Clera

Senior Silicon Engineer

San Francisco

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Clera first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included

Matched against 2.4M live jobs from 200,000+ employers in 200+ countries.

Tailor my resume for this job →

hirly's read of this role

Seniority
Senior
Stated salary
$200,000 – $300,000 per year
Country
US
Work mode
On-site / unstated
First seen by hirly
1 Oct 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

About the Role

As a founding silicon team member at a well-funded AI accelerator startup, you will lead the full journey of a custom XPU from FPGA prototype through tapeout and bring-up. This is a high-ownership, high-impact role that sets technical direction across architecture, RTL, verification, and tooling while the silicon organization grows around you.

What You'll Do

Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon.

Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code.

Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness.

Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic.

Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods.

Grow and mentor the silicon team as the company scales.

What We're Looking For

8 or more years of hands-on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs.

Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs.

End-to-end FPGA experience: RTL through synthesis, place-and-route, and deployment to working hardware.

Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture.

Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows.

Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools.

Background designing or optimizing AI accelerators or low-level AI kernel implementations.

Tapeout experience, high-speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages.

Self-directed, comfortable with ownership, and energized by fast-moving environments.

Compensation & Benefits

Base salary range: $200,000 to $300,000 USD annually , plus equity. Visa sponsorship is available.

Location

Full-time, on-site in San Francisco, CA . This role is not remote or hybrid.

Original posting on Clera's site ↗

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job