Silicon Engineer

About Anthropic

Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems.

About the role

Anthropic runs some of the largest AI training and inference workloads in the world, across multiple hardware platforms. We work from the chip level up with our silicon partners, and we are now deepening that investment by building a custom silicon team.

You will be one of a small number of people covering a large surface. We are opening searches across the key domains below, and we are interested in candidates whose center of gravity sits in any of them:

Front-end design

Pre-silicon verification

Physical design

Design for test

Analog and mixed-signal

Technology and foundry

CAD and design infrastructure

Packaging, signal integrity, and power integrity

This is a role for someone who has shipped silicon, has a realistic relationship with schedules, and is comfortable making consequential calls without a large organization behind them.

Key responsibilities

Take part in end to end activities for the program: strategy, specification, execution and the technical bar.

Write the specifications and interface definitions that others design against and keep them coherent as the architecture converges

Make and own directional calls: technology and IP selection, where we build versus buy versus license, and where we take design authority versus rely on partners

Build and share AI-assisted approaches to the code-like parts of your domain, and help the team learn what Claude can genuinely accelerate

Contribute to the architecture and micro-architecture discussion from your domain's perspective, including the tradeoffs your area imposes on the rest of the chip

Partner with Anthropic's inference, performance, kernels, and infrastructure teams on hardware-software co-design, and with our hardware systems team on bring-up and integration

Support first-silicon bring-up and debug when it arrives, regardless of which domain you came in through

Minimum qualifications

Deep, hands-on expertise in at least one silicon domain: front-end design, pre-silicon verification, physical design, design for test, analog and mixed-signal, technology and foundry, design infrastructure, or packaging and signal/power integrity

Direct personal contribution to silicon that taped out and shipped, with ownership you can speak to in detail

Working fluency in the domains adjacent to your own, sufficient to reason about chip-level tradeoffs outside your specialty

Experience working with external partners — ASIC houses, IP vendors, foundries, or test partners — including reviewing their work and holding a technical bar

Track record of owning directional technical decisions and their consequences, not only making recommendations

Practical experience using AI coding tools in your own work, and clear ideas about where they help and where they do not

Clear written and verbal communication, and experience driving alignment across teams and organizations

Comfort operating with high autonomy and little scaffolding on a highly dynamic program

Preferred qualifications

Experience on machine learning accelerators, high-performance compute, or other large, high-bandwidth designs

Experience on a founding or early-stage silicon team, including standing up flows, methodology, or tooling from nothing

Experience with both partner-executed and fully in-house programs, and a view on the tradeoffs between them

Familiarity with the chip-package-system interface and the tradeoffs that cross it

Experience with hardware-software co-design and working directly with compiler, kernel, or runtime teams

Experience building or extending AI-assisted design, verification, or physical design flows

Depth in memory subsystems, on-die interconnect, numerics, or low-power design

Representative projects

Writing the specification for a compute datapath and defending its numeric format strategy against the alternatives

Standing up front-end flows and release management from scratch, then handing releases to an ASIC partner on a fixed cadence

Running fast in-house place-and-route loops on a critical block and feeding PPA reality back into the architecture

Selecting and qualifying PHY IP, then validating it on first silicon

Building a formal verification methodology for a new block and deciding where formal earns its keep versus simulation

Defining test strategy and the automated-test-equipment handoff interface with our partner

Prototyping a Claude-assisted workflow for RTL review, coverage triage, or specification consistency checking, and reporting honestly on what it did and did not do

Debugging a first-silicon failure that crosses your domain and someone else's

The annual compensation range for this role is listed below.

For sales roles, the range provided is the role’s On Target Earnings ("OTE") range, meaning that the range includes both the sales commissions/sales bonuses target and annual base salary for the role.

Annual Salary:

$320,000 — $485,000 USD

Logistics

Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience

Required field of study: A field relevant to the role as demonstrated through coursework, training, or professional experience

Minimum years of experience: Years of experience required will correlate with the internal job level requirements for the position

Location-based hybrid policy: Currently, we expect all staff to be in one of our offices at least 25% of the time. However, some roles may require more time in our offices.

Visa sponsorship: We do sponsor visas! However, we aren't able to successfully sponsor visas for every role and every candidate. But if we make you an offer, we will make every reasonable effort to get you a visa, and we retain an immigration lawyer to help with this.

For roles performing work in California: We will consider for employment all qualified applicants, including those with arrest or conviction records or criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the San Francisco Fair Chance Ordinance, the City of Los Angeles’ Fair Chance Initiative for Hiring Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act.

We encourage you to apply even if you do not believe you meet every single qualification. Not all strong candidates will meet every single qualification as listed. Research shows that people who identify as being from underrepresented groups are more prone to experiencing imposter syndrome and doubting the strength of their candidacy, so we urge you not to exclude yourself prematurely and to submit an application if you're interested in this work. We think AI systems like the ones we're building have enormous social and ethical implications. We think this makes representation even more important, and we strive to include a range of diverse perspectives on our team.

Your safety matters to us. To protect yourself from potential scams, remember that Anthropic recruiters only contact you from @anthropic.com email addresses. In some cases, we may partner with vetted recruiting agencies who will identify themselves as working on behalf of Anthropic. Be cautious of emails from other domains. Legitimate Anthropic recruiters will never ask for money, fees, or banking information before your first day. If you're ever unsure about a communication, don't click any links—visit anthropic.com/careers directly for confirmed position openings.

How we're different

We believe that the highest-impact AI research will be big science. At Anthropic we w