hirly

Sec

SRAM Memory Design

SSIR, Angkor West, Bangalore, India

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Sec first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included

Matched against 2.4M live jobs from 200,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending. ChatGPT: manual setup today.

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority
Mid level
Country
IN
Work mode
On-site / unstated
First seen by hirly
27 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Position Summary

Position: SRAM Memory Design Engineer:

Roles and Responsibilities:

  • Design highly competitive circuits to meet performance/power specifications requested by customers
  • Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
  • Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design.
  • Own the responsibility from SPEC to GDS and DK delivery.
  • Review circuits, robustness reports and identify potential robustness issues.
  • Review Layouts and suggest improvement areas to achieve competitive PPA
  • Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
  • Must be able to communicate effectively across different teams.

Role and Responsibilities

Skills & Experience:

Master/Bachelor in electronics

Working experience in preferably Memory design

Understanding of RC network and FINFET fundamentals are necessary.

Custom or Compiler SRAM/ROM development experience

Fundamentals of process variability and its effect on memory design

Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)

Strong understanding of circuit design fundamentals

Critical path modelling concept, various type of models ( RC, C, Pai,ladder)

Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc

Analysing layout and understanding of LLE effects.

Skills and Qualifications

Experience – 4 to 10 Years of experience

Qualifications: B.Tech/B.E/M.Tech/M.E

Disclaimer: Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here .

Original posting on Sec's site ↗

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job