Advanced Packaging Process Engineer

Who We Are

Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.

What We Offer

Location:

Singapore,SGP

You’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more.

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As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.

Position Summary

Lead the development and integration of advanced packaging technologies, with a focus on Hybrid Bonding solutions for Logic, Memory, and 3D heterogeneous integration applications. Responsible for process development, technology innovation, and customer-driven solutions from concept through qualification.

Key Responsibilities

Develop and optimize end-to-end Hybrid Bonding processes, including wafer/die surface preparation, wet and dry cleaning, plasma activation, dielectric-to-dielectric bonding, Cu-Cu direct bonding, and post-bond annealing to achieve bonding yield, alignment, electrical performance, and reliability targets.

Design and execute process characterization and DOE studies to establish process windows, understand bonding mechanisms, and improve critical metrics such as bond strength, void density, overlay accuracy, Cu oxidation control, and interface quality.

Investigate and resolve process integration challenges related to CMP surface topography, surface chemistry, contamination control, pattern density effects, thermal budget, wafer / die warpage, and bonding defectivity through data-driven root cause analysis.

Collaborate with equipment, materials, metrology, and integration teams to develop scalable solutions for die-to-wafer (D2W) Hybrid Bonding applications supporting HBM, Logic, and 3D heterogeneous integration technologies.

Define and implement characterization methodologies using optical inspection, IR imaging, SEM, AFM, XPS, contact angle measurement, electrical test, and reliability evaluation to monitor process performance and qualify new technologies.

Support development of advanced packaging technologies including HBM, Logic, TSV, RDL, and die-to-wafer bonding.

Engage customers, research institutes, and ecosystem partners on joint technology development projects.

Generate technical reports, patents, publications, and technology roadmaps.

Qualifications

Bachelor's, Master's, or PhD in Engineering, Materials Science, Physics, or related disciplines.

Minimum 5 years of semiconductor experience in technology development, process integration, or advanced packaging.

Hands-on experience in one or more of the following:

Advanced Packaging

Hybrid Bonding

CMP

Plasma Processing

Wet Cleaning

TSV Integration

Process Integration

Preferred Skills

Strong understanding of Hybrid Bonding mechanisms and package integration flows.

Experience with DOE, JMP/Minitab, and statistical process analysis.

Knowledge of reliability, failure analysis, and advanced metrology techniques.

Work Location

Science Park II (Moving to Tampines office starting Apr 2027)

Additional Information

Time Type:

Full time

Employee Type:

Assignee / Regular

Travel:

Relocation Eligible:

No

Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.