hirly

Broadcom

Analog and Mixed Signal Design Engineer

USA-AZ-Chandler-North Juniper Drive · USA-CA Irvine Alton Parkway Bldg 1

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Broadcom first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included

Matched against 2.6M live jobs from 210,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude or ChatGPT and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending.

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority
Mid level
Stated salary
$109,700 per year
Country
US
Work mode
On-site / unstated
First seen by hirly
27 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Role Overview

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

Responsibilities

  • Circuit Design & Verification: Design schematic architectures for analog and mixed-signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.
  • Layout & Post-Layout Validation: Supervise layout design and verify post-layout design using SPICE simulations to ensure silicon success.
  • Digital Modeling: Build behavioral and gate-level models for IPs and validate functionality through Verilog simulations.
  • IP Delivery & Documentation: Create standard EDA tool views (including timing models), and author comprehensive datasheets and technical integration documents.
  • Silicon Bring-up & Validation: Establish post-silicon testing guidelines and oversee the validation process by analyzing and reviewing test data.

Education & Experience

  • MS or PhD in Electrical Engineering
  • 6+ years of mixed-signal and analog design experience.

Design Expertise

  • Deep knowledge of core analog concepts including gain, bandwidth, stability, device physics, circuit reliability, process variation, and the statistical analysis of Monte Carlo simulation results.
  • Strong understanding of layout effects on circuit performance.
  • Familiarity with Verilog modeling, digital circuits, and standard digital implementation flows.

EDA Tools

  • Proficiency with Cadence Virtuoso and simulation platforms like Spectre, HSPICE, or PrimeSim.
  • Experience with Synopsys PrimeTime and Verilog simulators such as Xcelium or VCS.

Professional Attributes

  • Excellent communication and teamwork skills.
  • Proven ability to independently navigate complex, new, or unfamiliar engineering challenges.

Desired Skills

  • Prior experience building and delivering mixed-signal IPs.
  • General familiarity with laboratory testing methodologies and common bench equipment to effectively guide lab teams.
  • Proficiency in scripting languages (Python, Perl, SKILL) to automate design and verification tasks.
  • Familiarity with ESD (Electrostatic Discharge) and latch-up design rules.
  • Silicon Failure Analysis (FA) and debugging skills.

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Original posting on Broadcom's site ↗

Listed on hirly, a job board. hirly is not the employer: Broadcom is hiring for this role.

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job