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Ceremorphic Technologies

ASIC Design Engineer

Hyderabad

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hirly's read of this role

Seniority
Mid level
Country
IN
Work mode
On-site / unstated
First seen by hirly
23 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

About the Role

Looking for candidates to work on digital design of high performance and low power Microprocessor / Machine Leaning Processor / Logic Designs

Key Requirements

  • Hands-on experience in architecture, microarchitecture, and logic design.
  • Expertise in AHB/AXI based SoC Architectures.
  • Strong knowledge in ARM M-series or A-Series MCU, RISC-V architectures and sub-system integration.
  • Experience in designing high-speed interfaces like USB, PCIe 4x/5x, Ethernet, Mobile DDR, Quad/Octa-SPI.
  • Strong experience in peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
  • Strong experience in signoff flows including lint, CDC, Synthesis, LEC and STA timing closure.
  • Hands-on experience in low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling).
  • Testability experience of Test Modes, DFT, MBIST and BScan.
  • VLSI implementation experience in synthesis, timing analysis, Design for Test and Memory BIST.
  • Senior positions require experience of designing processors / logic sub-systems for embedded, applications and machine learning processors.
  • Management positions require independent proven experience of owning and delivering Systems-on-Chip (SoC) products.
Original posting on Ceremorphic Technologies's site ↗

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