Broadcom

ASIC VERIFICATION ENGINEER

IND-Bangalore Electronic City - S1

hirly Pro

Get in front of the people hiring at Broadcom

Reach the hiring manager at Broadcom on LinkedIn, from your own account
hirly applies to this job for you, with unlimited applications
A resume and cover letter written for this job, unlimited
The hiring manager and recruiter at Broadcom, with contact details

Get Pro for this job →

$49 a month · ₹1,999 for 30 days in India · cancel any time

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

Keywords matched to this posting
Fit score before you apply
Cover letter included

Matched against 3M live jobs from 220,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude or ChatGPT and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending.

See how it works

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority: Mid level
Country: IN
Work mode: On-site / unstated
First seen by hirly: 27 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Job Description

What You can Expect -

- Work on Latest cutting edge CSG Switches.

- To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem.

- Develop and maintain verification Environment in Mix of SV/UVM.

- Understanding of the End to End spec along with Network & System topology.

- Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level.

- Coverage Closures, Gate Level Simulations along with end to end verification cycle.

What we are looking for -

- Bachelor's/Masters/PhD with Verification experience of 8+ years

- Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST

- Exposure to any one of the scripting languages - Perl or Python or SED/Awk

- Expertise in Co-Simulations (HW/SW) Flow and debugs

- Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary.

- Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0

- Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc

- Experience in GLS, Coverage Driven Methodology, ATE

- Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper.

- Exposure to Test Bench Accelerators /Emulation Platforms.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Original posting on Broadcom's site ↗

Listed on hirly, a job board. hirly is not the employer: Broadcom is hiring for this role.

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job