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Baidu USA

CPU Design Architect / Principal Digital Design Engineer

Sunnyvale, CA

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hirly's read of this role

Seniority
Lead / management
Country
US
Work mode
On-site / unstated
First seen by hirly
28 Sept 2026

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the posting

  • Job Description:
  • Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in:
  • - Perform CPU development and design integration for MIPS CPU subsystem.
  • - Explore latest technologies and be responsible for conducting fundamental research on new directions in CPU architecture
  • - Contribute ideas for advanced CPU performance features - analyze workloads in details, identify performance bottlenecks and opportunities, bring a data driven approach to tradeoffs in CPU design, derive architecture and micro-architecture to design/model implantation team, and bring ideas to successful silicon
  • Minimum Qualifications:
  • - Master Degree in Electrical Engineering, Computer Science or Computer Engineering.
  • - At least 5 years of CPU related Architect/RTL/Verification/Implementation design experience
  • - Knowledge and practical experience with common RISC CPU architecture.
  • - Familiarity with chip digital design flow, including RTL integration, simulation, STA.
  • - Understanding of high performance techniques and trade-offs in a CPU microarchitecture
  • - Ability to problem solve and prove own ideas
  • Preferred Qualifications:
  • - PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS
  • - 8+ years of CPU related Architect/RTL/Verification/Implementation design experience
  • - Strong CPU architecture knowledge and micro-architecture knowledge
  • - Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture.
  • - Familiarity with synthesis, power analysis and post silicon debugging
  • - Cross-site working experience is a PLUS.
  • - Common knowledge in modeling/DV/OS is a PLUS.
  • - Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.

#LI-DNI

Original posting on Baidu USA's site ↗

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