Design / DFT Director (NVE Engineering)

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Department Introduction

The Non-Volatile NAND Design Engineering organization is responsible for the architecture, design, integration, and optimization of analog, digital, mixed-signal, and test solutions enabling advanced NAND Flash memory products. Close collaboration across global design, technology, product, test, and manufacturing teams ensures scalable, manufacturable, reliable, and cost-effective products across technology generations.

Position Overview

We are seeking an expert and innovative Director of NAND Design for Test (DFT) to lead the global DFT strategy, architecture, and execution for advanced NAND Flash products at Micron Semiconductor Italia.

In this senior leadership role, you will define the DFT vision and technical roadmap, owning architecture, methodology, integration, verification, coverage closure, and build sign-off from early product definition through silicon initialization, validation, and mass production.

You will combine deep semiconductor and DFT expertise with strong interpersonal and people leadership, partnering with Design, Product Engineering, Test, Probe, Quality, Failure Analysis, Technology Development, and Manufacturing to improve product quality, yield, cost, test time, reliability, and time to market.

AI, machine learning, and data analytics are a core pillar of this role. You will lead adoption across the DFT organization and transform the delivery of testability, diagnostics, and silicon learning at scale. You will build and scale a high-performing distributed and international group.

Responsibilities

Responsibilities include, but are not limited to:

Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations; anticipate future requirements and establish scalable architectures, methodologies, technical priorities, success metrics, and governance aligned with quality, cost, performance, and schedule objectives.

Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out; lead scalable testability, diagnostic, design-for-debug, and embedded test solutions across digital logic and custom circuits, ensuring predictable delivery and clear coverage, test-time, area, power, quality, and execution targets.

Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs; work with Product Engineering, Test, Probe, Failure Analysis, Quality, Technology Development, and Manufacturing through silicon bring-up, qualification, and high-volume production to achieve quality, coverage, yield, reliability, test-time, cost, and time-to-market objectives.

Drive reusable methodologies, automation, and DFT and design-for-debug innovation; strengthen simulation-to-silicon correlation, diagnostics, and root-cause resolution, with measurable improvements in debug efficiency, silicon learning, test quality, test time, yield learning, product cost, and time to market.

Build, develop, and inspire a high-performing global DFT organization; develop managers and senior technical leaders through mentoring, talent development, performance management, succession planning, and career growth. Allocate priorities and resources across complex programs, communicate strategy, plans, decisions, risks, and results to senior partners, and sustain technical depth, AI and data skills, leadership capability, engagement, and retention within an inclusive, high-trust engineering culture.

AI Enablement and Productivity

AI, machine learning, and data analytics are a core leadership responsibility, not an optional productivity tool. The Director will define and lead the AI/ML strategy for DFT and scale adoption across the global organization, with measurable engineering and product outcomes:

Deploy data-driven and AI-assisted solutions for test-pattern and test-flow optimization, fail diagnosis and root-cause analysis, yield prediction, coverage analytics, and test-time reduction.

Establish reusable AI-enabled DFT, diagnostic, and analytics workflows; measure gains in debug time, test time, yield learning, engineering productivity, quality, and execution speed.

Build AI and data-analytics capabilities across the team and partner across functions to evaluate, adopt, and scale emerging tools and methodologies supporting future NAND technology generations.

Minimum Qualifications

M.S. or Ph.D. in Electrical Engineering, Electronics, Computer Engineering, or a related field.

Significant experience in semiconductor design, DFT, product test, or silicon validation, including leadership of sophisticated engineering programs and teams. Demonstrated success defining strategy and delivsophisticatedomplex products from concept through tape-out, silicon validation, and large-scale manufacturing.

Deep knowledge of NAND design, verification, DFT principles, test architecture, coverage analysis, silicon debug, and semiconductor manufacturing flows.

Proven people leadership, including organization building, talent development, performance management, and leading through other managers or senior technical leaders. Strong multi-functional influence, executive communication, technical decision-making, and program execution skills in a global environment.

Solid understanding of AI/ML and data-analytics techniques and their practical application to semiconductor design, test, or manufacturing. Proficiency with engineering automation; working knowledge of scripting or programming languages such as Python and C/C++.

Preferred Qualifications

Experience with NAND Flash or other non-volatile memory technologies and their design, test, reliability, and manufacturing challenges.

Experience with memory test algorithms, embedded self-test/diagnostics, custom-circuit DFT, firmware-to-hardware test interfaces, and production test optimization.

Hands-on experience deploying AI, machine learning, or sophisticated analytics in production environments for design verification, coverage, silicon debug, yield, or test optimization.

Track record of improving test quality, yield learning, test time, product cost, or time to market through methodology and interpersonal innovation.

Experience leading geographically distributed teams and collaborating with external EDA, IP, equipment, or technology partners.

The base salary range that Micron estimates it could pay in for this position full-time is:

• 105.000,00 € - 183.000,00 € per year, with A1-D CCNL Level.
• Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for the position.

In addition to base pay, the remuneration package also includes: eligibility for a variable plan subject to the personal achievement of objectives and the company's performance, and benefits, which -at the discretion of the company- currently include meal vouchers, corporate welfare, yearly allowance of remote working days, supplementary health insurance, life coverage, Employee Assistance Program. Please refer to this page to check our current benefit offering: EMEA Benefits

All qualified applicants will receive consideration f