DFT Engineer

NVIDIA is seeking a highly motivated DFT Engineer to join our silicon engineering team. In this role, you will work closely with Design, Test, CAD, and Silicon Engineering teams to validate and debug Design-for-Test (DFT) features in some of the industry's most advanced GPUs and SoCs.

This position offers an excellent opportunity to learn industry-leading DFT methodologies and contribute to cutting-edge products powering AI, accelerated computing, and next-generation platforms.

What you'll be doing

• •Verify DFT features and test infrastructures, including Scan, MBIST, JTAG, and related functionality.
• •Collaborate with Design, Integration, CAD, and Test Engineering teams to define verification scope and test strategies.
• •Execute verification and validation activities at the IP, subsystem, and full-chip levels.
• •Perform RTL and gate-level debugging to identify and resolve design and test issues.
• •Generate and validate test patterns and support silicon bring-up and debug activities.
• •Improve engineering productivity through scripting, automation, and workflow enhancements.
• •Support verification flow and methodology improvements.

What we need to see

• •1+ years of experience with an M.S. degree in Electrical Engineering, Electronics Engineering, Microelectronics, IC Design, or a closely related discipline.
• •Strong understanding of digital circuits, computer architecture, and semiconductor design fundamentals.
• •Strong analytical, problem-solving, and debugging skills.
• •Familiarity with RTL simulation and debug tools such as Verdi and VCS.
• •Basic understanding of SoC architecture, including clocking, reset, power, and I/O concepts.
• •Programming or scripting experience with Python, Tcl, Perl, C, or C++.
• •Fluent verbal and written communication skills in English.
• •Strong teamwork skills and willingness to learn in a fast-paced environment.

Ways to stand out from the crowd

• •Understanding of DFT methodologies, including Scan, ATPG, MBIST, JTAG, and Boundary Scan.
• •Experience with RTL or gate-level simulation and debugging.
• •Familiarity with silicon bring-up, hardware validation, or failure analysis.
• •Experience developing automation tools and engineering workflows.
• •Exposure to AI-assisted engineering tools, machine learning, or data analytics.