hirly

ZEISS

FPGA Developer (f/m/x)

Oberkochen

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hirly's read of this role

Role family
Engineering
Seniority
Mid level
Country
DE
Work mode
On-site / unstated
First seen by hirly
3 Oct 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Your Role:

Design and implement FPGA-based digital logic using hardware description languages such as VHDL or Verilog

Develop and integrate FPGA modules, including custom IP cores, communication interfaces, and control logic

Analyse system requirements and translate them into efficient and maintainable FPGA realisations

Perform functional simulation, timing analysis, verification, and validation of FPGA designs

Debug and troubleshoot FPGA implementations using simulation and hardware debugging tools

Optimise FPGA designs for timing closure, resource utilisation, power consumption, and performance

Implement and verify high-speed interfaces and protocols such as PCIe, Ethernet, and memory interfaces

Collaborate with FPGA architects, hardware engineers, software developers, and system architects to ensure seamless system integration

Create and maintain technical documentation, including design specifications, interface descriptions, test plans, and verification reports

Participate in design reviews and contribute to reusable FPGA platforms, coding standards, and development best practices

Actively share knowledge and support the continuous improvement of FPGA development methodologies, tools, and workflows

Your Profile:

Successfully completed studies in electrical engineering, computer engineering, communications engineering, computer science, or a comparable field

Solid experience in FPGA development using VHDL and/or Verilog

Strong understanding of digital design principles, FPGA architectures, synchronous systems, and clock domain crossing concepts

Experience with FPGA development environments such as Xilinx Vivado, Intel Quartus, or similar toolchains

Knowledge of simulation and verification methodologies using tools such as ModelSim, QuestaSim, OSVVM, or UVM

Experience with timing analysis, timing closure, debugging, and performance optimisation of FPGA designs

Familiarity with high-speed communication interfaces and protocols such as PCIe, Ethernet, DDR, or comparable technologies

Understanding of system integration and collaboration within interdisciplinary hardware and software development teams

Strong analytical and problem-solving skills combined with a structured and quality-oriented working style

High level of initiative, ownership, and commitment to delivering reliable FPGA solutions

Excellent teamwork and communication skills

Proficiency in German and English, both written and spoken

Enthusiasm for developing innovative solutions in a high-tech environment

Your ZEISS Recruiting Team:

Andre Grunzel, Matthias Sonnentag

Original posting on ZEISS's site ↗

Listed on hirly, a job board. hirly is not the employer: ZEISS is hiring for this role.

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