hirly

Altera

FPGA IP Design and Verification Engineer

Regus, Madhapur

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Altera first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included

Matched against 2.4M live jobs from 200,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending. ChatGPT: manual setup today.

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority
Mid level
Country
IN
Work mode
On-site / unstated
First seen by hirly
22 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Job Details:

Job Description:

Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Qualifications:

7+ years of experience in Semiconductor IP Design verification.

Familiarity with HDL languages (VHDL, Verilog, SystemVerilog ).

Experience or knowledge in scripting languages such as Tcl , Perl, or Python.

Prior experience or exposure to FPGA tools (Quartus or Vivado ) would be advantageous .

Strong willingness to learn new skills and technologies.

Ability to work collaboratively within a team environment.

Good communication skills and ability to clearly present project details and outcomes.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Regus, Madhapur

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Original posting on Altera's site ↗

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job
FPGA IP Design and Verification Engineer – Altera | hirly.me