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Ceremorphic Technologies

FPGA Prototyping/Emulation Engineer

Hyderabad

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hirly's read of this role

Seniority
Mid level
Country
IN
Work mode
On-site / unstated
First seen by hirly
23 Sept 2026

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the posting

About the Role

The candidate would own and drive the design, implementation, and verify FPGA prototypes of next-generation SOCs. The responsibilities mainly cover the following:

  • FPGA integration and implementation of All interfaces (PCIe, DDR, etc)
  • FPGA implementation and timing closure
  • Provide emulation Platform solution for FW development
  • Provide emulation Platform for Pre silicon Validation
  • FPGA Validation and debug

Key Requirements

  • Hands on design experience using Verilog, System Verilog and porting large designs to FPGA including combination of custom RTL as well as proven IP cores.
  • FPGA experience includes implementation, synthesis (Synplify/Vivado), timing closure using Vivado.
  • Ability to partition a big AISC design into multiple FPGA sub-systems and implement modules for interconnection between these sub-systems.
  • Proficiency in Perl, Tcl language.
  • Good hardware debug skills using FPGA debug tools like Chipscope and lab debug equipment like Oscilloscopes and Logic Analyzers to root cause issues at silicon or board level.
  • Hands on experience using PCIe controller, DMA and working knowledge of AXI protocols and ARM is required
  • Ability to work closely with software team and get involved in hardware-software co-debug.
Original posting on Ceremorphic Technologies's site ↗

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