HSIO PHY Verification Engineer

Job Type: Full Time

Job Location: Bangalore

Experience: 6-12 years

Job Responsibilities:

• •HSIO PHY Integration verification @ Sub-system and SoC level
• •HSIO PHY IP level test case porting to SoC level
• •HSIO PHY SoC level Test case development, Running regression in RTL/GLS & Timing simulations
• •HSIO PHY Virtual tester simulations in RTL/GLS & Timing simulations
• •Hands-on experience in System Verilog, OVM/UVM based constrained random verification.
• •Experience with scripting languages like Python, Perl, skill, tcl or equivalent to automate flows is a plus.
• •Hands on Testbench bring up, integrating third party VIPs, digital design, verification, debugging, and waveform debug
• •Knowledge on USB2/USB3/PCIE/UFS/MIPI/DDR PHY's functionality & Loopback tests concepts
• •Knowledge on SoC level Interface/Configurability of HSIO PHY Registers
• •Knowledge on HSIO PHY Controller and PHY + controller test case porting knowledge
• •Generate of EVCD/Bench collaterals for target test cases
• •Partner with ATE/Bench team on Silicon bring up
• •Strong communication skills to interact with a global team.

Skills: rtl verification , Regression Testing, Test Case Development, Uvm, systemverilog

Experience: 6.00-12.00 Years