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Cadence

Intern - Design Engineering

SHANGHAI

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hirly's read of this role

Seniority
Internship
Country
CN
Work mode
On-site / unstated
First seen by hirly
5 Nov 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • About the team:
  • Our team deliver many high-performance products based on the industry’s advanced technology with high frequencies up to 6400MHz. Our product processes include TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
  • Focus on high speed digital DDR and HBM/UCIe/PCIe/eUSB IPs physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.

实习 - 数字后端工程师 (工作地点：上海)

  • 职位描述：
  • (1)芯片物理设计, 后端布局布线，STA，物理验证等。
  • (2)团队合作，负责电路后端设计及交付，设计质量和进度控制
  • 职位需求：
  • (1)微电子,电子工程硕士以上学历
  • (2)较强的问题分析以及团队合作能力
  • (3)较强的中英文口语沟通及写作能力
  • (4)熟悉数字后端工具
  • (5)积极主动, 有责任心

**每周可以工作至少3天，实习期6-8个月

We’re doing work that matters. Help us solve what others can’t.

Original posting on Cadence's site ↗

Listed on hirly, a job board. hirly is not the employer: Cadence is hiring for this role.

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