hirly

Cadence

Lead Customer Engagement Engineer

SHANGHAI

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Cadence first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included

Matched against 2.3M live jobs from 200,000+ employers in 200+ countries.

Tailor my resume for this job →

hirly's read of this role

Seniority
Lead / management
Country
CN
Work mode
On-site / unstated
First seen by hirly
29 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an integral member of the HSV Customer Support Team, you will work with our customers and field AE teams and R&D groups to provide technical support for our Palladium, Protium and Virtual Protocol (PDAPP) products. You will enjoy the experience and challenge in working with a broad spectrum of designs and customers.

Responsibilities includes:

  • Taking ownership and quickly drive to resolution product issues reported by field AEs and customers.
  • Debug customer reported failures, produce test cases to replicate failure and log issues with HSV R&D teams.
  • Recommend potential workaround or application level solutions to customers when necessary.
  • Test R&D fixes/patches.
  • Work with customer and internal groups to spec out enhancement requests.
  • Testing new product features for future s/w releases or h/w platform, including participation in internal beta activities.

Position Requirements:

  • Requires a BS-EE/CE (MS-EE/CE preferred) with a minimum of 5 years experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
  • Strong knowledge of design debug techniques and a strong understanding in logic design.
  • Knowledgeable in verification methodologies for complex EDA environments.
  • Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.
  • Proficiency in Unix/Linux scripting languages (ksh/bash/csh).
  • Proficiency in PCIe, USB and Ethernet protocol.
  • Proficiency in TBA, SVA, SV coverage, Low Power(UPF). UVM experience is a plus.
  • Experience with emulation, Cadence's Palladium product preferred.
  • Excellent communication skills. Must have ability to communicate complex issue to internal teams and customers in a clear and concise manner.
  • Occasional travel may be required to resolve critical customer issues.
  • undefined

We’re doing work that matters. Help us solve what others can’t.

Original posting on Cadence's site ↗

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job