Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Tensilica CPU/DSP Processor Team is hiring senior engineers to join our R&D teams in Pune, Bangalore and Noida. This is an amazing opportunity to work in an impactful job at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great Processor team where you can make an impact that is visible.

• Lead Engineer positions are for one of the two roles:
• (a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
• (b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Required Skills and Experience :

• •4+ years of Design or Design Verification experience
• •BS/MS in EE/Computer Engineering or a similar major.
• •Deep understanding of Digital Design and/or Design Verification fundamentals
• •Experience in working as part of a team, or guiding/mentoring junior engineers
• •Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
• •Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
• •Good working knowledge of scripting languages like Python, Perl, Tcl, Unix shell or similar languages
• •Knowledge of technical safety concepts and requirement specifications according to ISO 26262
• •Proficient with C language and assembly language
• •Excellent written and oral communication skills necessary
• •Exposure to debugging netlist/gate level simulation.
• •General understanding of embedded SW.

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