Member of Technical Staff, ASIC Design

About Netpreme

The biggest bottleneck in AI systems today is memory. Chips compute faster than they can be fed data—a problem known as the memory wall—and Netpreme is building the solution that allows AI memory to scale independently of AI compute. Our approach spans the full stack, from a proprietary memory management framework at the XPU kernel and OS levels to X-Mem™, the world’s first Memory Processing Unit (MPU) silicon. Founded by MIT researchers at the intersection of optical networking, ML systems, and GPU kernel optimization, we’re based in Cambridge, MA, and Santa Clara, CA. We’re looking for people who want to own hard problems end to end—and help shape the next generation of AI systems.

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About The Role

We are seeking experienced Senior ASIC Designers.

This role demands proven technical expertise in advanced ASIC design flows, and leadership in execution, cross-functional coordination, and final product delivery. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.

This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

The Opportunity

Impact: AI is advancing faster than the infrastructure underneath it. We’re working at that layer, unlocking more capability from every GPU while dramatically improving efficiency. The work you do here compounds across state-of-the-art models, systems, and real-world applications.

Timing: Joining now means real ownership, including equity, and a direct say in product direction. You’ll work from first principles, move quickly from insight to execution, and see your work show up in what we ship, not just in a roadmap.

Culture: We care about rigor, clarity, and impact. Disagreement is welcome when it’s thoughtful, the best idea wins regardless of who it comes from, and you’ll learn something new most weeks.

Your Impact

As part of the Silicon Design Team, responsible for RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.

Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.

Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.

Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.

Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.

Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Minimum of 5+ years of ASIC/SOC digital design experience

Excellent leadership, communication, team building and stakeholder management skills.

Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.

Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.

Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.

Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.

Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).

Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.

Design and tapeout of any advanced silicon device is highly preferred.

Nice to Have

PhD in Electrical Engineering, Computer Engineering, or a related field.

Experience managing relationships with external design partners, IP vendors, and foundries.

Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.

What We Offer

Competitive salary with performance-based bonus and early-stage equity grant

100% employer-paid Health, Dental, and Vision coverage for you and your dependents

401(k) match with immediate vesting, and access to financial advisors to help you reach your financial goals

100% employer-paid Life, Disability, and AD&D insurance, plus a fitness stipend and wellness & mental health perks

Generous PTO: 20 vacation days, 15 company holidays (including 3 floating days of your choosing)

Daily lunch stipend

Enterprise-level Claude & ChatGPT access with a generous token budget

Well-equipped, sunny offices in Santa Clara, CA & Cambridge, MA with on-site parking and EV charging; on-site fitness center in Santa Clara; gym discounts near our Cambridge office

Visa sponsorship and relocation assistance to one of our office hubs

A collaborative, continuous-learning environment with smart, dedicated colleagues building the next generation of high-performance computing architecture