Micro-Optics Engineer

Role Overview

We are seeking a Senior Micro-Optics/Microlens Array Engineer to design, model, and validate microlens-array and wafer-level micro-optical components for high-density photonic packages. You will translate system-level optical requirements into manufacturable designs, build tolerance budgets, work with fabrication and packaging partners, and close the loop with measured data.

Candidate note: We do not expect one person to match every item below. Strong candidates from micro-optics, optical packaging, semiconductor photonics, lithography/process integration, precision optics, or FDTD-Zemax co-design backgrounds are encouraged.

What You Will Do

Own micro-optical design: design microlens arrays and compact micro-optical components, including lens pitch, aperture, focal length, numerical aperture, sag, surface form, fill factor, array uniformity, substrate, material, and coating choices.

Build connected optical models: use tools such as Zemax OpticStudio, Code V, FRED, LightTools, VirtualLab, Ansys/Lumerical, COMSOL, or equivalent; combine ray, physical-optics, diffraction, and statistical methods where appropriate.

Bridge EM-scale and package-scale design: where useful, connect FDTD, FEM, EME, RCWA, or similar electromagnetic simulations to Zemax/Code V/physical-optics models so local optical-interface behavior is represented in system-level trade studies.

Drive tolerancing and yield: develop sensitivity studies and tolerance budgets across fabrication, placement, package stack-up, adhesive, thermal, refractive-index, coating, and surface-form variation; use Monte Carlo and DOE methods to connect design choices to expected yield.

Bring semiconductor process awareness: partner with process and supplier teams across lithography, grayscale/direct-write patterning, imprint, etch transfer, deposition, thin-film coatings, wafer-level metrology, design rules, and process-window trade-offs.

Translate design intent: create vendor-ready specifications, optical prescriptions, mechanical drawings and guidance, material and coating requirements, metrology plans, incoming inspection criteria, and acceptance criteria.

Partner with suppliers: evaluate fabrication routes such as photoresist reflow, grayscale lithography, etch transfer, molding, and replication.

Validate hardware: plan and run prototype characterization, including surface profile, focal length, array uniformity, optical throughput, reflection behavior, polarization sensitivity, thermal drift, environmental stability, and alignment sensitivity.

Automate the workflow: build Python tools for simulation sweeps, tolerance studies, data reduction, visualization, dashboards, and clear technical reporting.

Work cross-functionally: partner with packaging, mechanical, thermal, test, reliability, device, and system teams to move designs from concept to qualified hardware.

What Will Help You Succeed

This section is a guide, not a rigid checklist. We care most about evidence of technical ownership, sound physics, manufacturability judgment, and the ability to learn quickly.

M.S. or Ph.D. in Optical Engineering, Electrical Engineering, Applied Physics, Physics, Photonics, Mechanical Engineering, Materials Science, or a related field; B.S. with exceptional relevant experience also considered.

Industry experience in micro-optics, wafer-level optics, optical design, photonic packaging, optomechanics, precision optics, semiconductor process integration, or advanced optoelectronic hardware.

Experience designing microlens arrays, aspheric micro-optics, diffractive or hybrid micro-optical surfaces, compact optical elements, or package-level optical features with manufacturing constraints.

Proficiency with optical modeling and tolerancing in Zemax OpticStudio, Code V, FRED, LightTools, VirtualLab, Ansys/Lumerical, COMSOL, or equivalent.

Nice to have: FDTD-Zemax co-design experience, or equivalent EM-to-system optical modeling, especially where simulation outputs inform tolerances, angular/spectral response, surface geometry, or package-level decisions.

Nice to have: working knowledge of semiconductor processing or microfabrication, including lithography, etch, deposition, thin films, wafer-level metrology, process variation, design rules, or DFM.

Ability to convert requirements into an optical design, tolerance budget, supplier data package, and practical characterization plan.

Experience with prototype characterization, failure analysis, design iteration, and model-to-hardware correlation.

Python skills for simulation automation, numerical analysis, data reduction, and reporting.

Clear written and verbal communication; ability to operate independently in a fast-changing startup environment.

Helpful Experience

Taking wafer-level optics or micro-optical components from concept through prototype builds, supplier qualification, or production ramp.

High-density optoelectronic packages, semiconductor photonics packages, optical interconnect hardware, co-packaged optics, sensing systems, LiDAR, AR/VR optics, miniature imaging, or datacom hardware.

Semiconductor process collaboration: mask or layout review, critical-dimension data, SEM/AFM/profilometry interpretation, film-stack review, process-control limits, or interaction with a foundry/process team.

DFM, DVT, reliability screening, thermal cycling, humidity exposure, high-temperature storage, and environmental qualification.

Optomechanical CAD or GD&T using SolidWorks, NX, Creo, Zemax CAD exchange, or equivalent.

Lab automation with motion stages, cameras, optical power meters, OSAs, temperature controllers, SMUs, oscilloscopes, Python/PyVISA, SCPI, or LabVIEW.

How You Will Work

Owner mindset: drive ambiguous technical problems from first principles to measured hardware.

Bias for action: build lightweight experiments, define clear metrics, and iterate based on data.

Cross-functional fluency: communicate trade-offs across optics, semiconductor process, packaging, mechanical, thermal, test, reliability, and systems teams.

Builder mentality: create reusable models, scripts, specifications, and test methods.