hirly

Phinity Labs

Physical Design Lead

San Francisco

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Phinity Labs first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included
Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending. ChatGPT: manual setup today.

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Role family
Design
Seniority
Lead / management
Country
US
Work mode
On-site / unstated
First seen by hirly
9 Oct 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Phinity is an AI research lab focused on solving chip design. The bottleneck to AGI is compute, and we enable AI agents to tape-out chips autonomously, from architecture to post-silicon. We are building RL environments, agent infrastructure, and evaluation systems to accomplish this. Our team brings together deep AI and silicon expertise, including leaders and executives from top chip companies, post-training chip-design models at NVIDIA, AI for formal verification research, previous exits, and over 10 years of experience building chips at NVIDIA, Intel, Mediatek, and others.

We are hiring a Physical Design Lead .

You will be responsible for:

Leading PD flows and optimization of block-level to full-chip level optimizations

Define Synthesis to layout flows, including PDN, clock-trees, PVT corners and custom cell definitions. Responsible for implementing characterization flows for custom cells and memory blocks.

Responsible for executing IP and Fullchip design optimizations working with PD engineers. Identify areas of optimization in design utilization, power grid and clock network within the design.

Responsible for delivering tapeout ready design optimized for the target PPA, and utilizing the in-house capability on prompt-to-GDS.

Why Phinity

Work directly with the founders to shape the strategy and growth of an ambitious AI research lab

Take ownership of high-impact initiatives across business strategy, partnerships, and company operations

Collaborate with leading AI researchers and hardware experts at the frontier of autonomous chip design

Benefits include

Health insurance

Retirement plans

Unlimited PTO

Paid parental leave

Lunch and dinner provided in-office

Original posting on Phinity Labs's site ↗

Listed on hirly, a job board. hirly is not the employer: Phinity Labs is hiring for this role.

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job