Research associates (m/f/x)

In order to fill a fixed-term position in full-time (39.83 hours/week) starting January 1st, 2027, we are looking for two

Research associates (m/f/x)

We are an international team engaged in teaching and research on approximate computing, reconfigurable accelerators for machine learning applications, design automation for emerging technologies, reliability, and fault tolerance of (multi-) processor and embedded systems. In particular, we investigate the dynamic reconfiguration of systems for energy efficiency. Within the BMFTR-funded research project EURO-NPU, we are developing the next generation of ultra-efficient edge AI processors. The project aims to rethink rigid AI accelerators by exploring dynamically reconfigurable architectures that flexibly adapt their precision, approximation levels, and early-exit paths to energy budgets and workloads at runtime. In the EURO-NPU consortium (consisting of 11 industry and academic partners), RUB leads the technical and organizational coordination as well as the NPU architecture design. We are offering two PhD positions whose research topics include NPU architecture design, HW/SW co-design, SoC system integration, and physical silicon implementation. You will have the creative autonomy to investigate novel microarchitectural paradigms, approximate arithmetic, and model co-design, while gaining invaluable experience by taking these academic concepts through to a physical ASIC tapeout of a chip prototype in collaboration with consortium partners. Depending on your strengths and interests, you can specialize in specific research directions within the project.

• Scope: full-time
• Duration: fixed-term, 3 years
• Start: starting January 1st, 2027
• Apply by:

Your tasks:

• •Architectural Research and NPU Innovation: Research and formulate novel bitwise, systolic dot-product array architectures capable of dynamically switching quantization bit-widths (multi-precision) and approximate computing (AxC) units at runtime. Investigate internal microarchitectures, command stream-based control mechanisms, and architectural protection primitives.
• •Prototyping and System-Level Research: Embed the NPU core into a full SoC platform (including RISC-V CPUs, AXI interconnects, and peripherals). Perform research-driven Design Space Explorations (DSE) and Power, Performance, and Area (PPA) analyses under realistic application workloads.
• •Silicon Realization and Physical Validation: Bridge academic theory with physical realization by preparing verified RTL frontends and IP documentation for a 22nm GlobalFoundries ASIC tapeout. Perform post-silicon validation and characterization to benchmark physical chip measurements against theoretical models.
• •HW/SW Co-Design and Algorithmic Exploration: Conduct fundamental research on the interplay between dynamic precision scaling, model accuracy, and system resilience. Develop novel algorithms and co-design strategies to embed hardware guarantees (e.g. regarding real-time, security, or accuracy) directly into NN models.
• •Scientific Dissemination: Publish research findings in top-tier international peer-reviewed EDA, computer architecture, and hardware design conferences and journals.
• •Research Ownership: Take ownership of your PhD research topic, formulate and test original scientific hypotheses, and work independently while collaborating with academic and industrial consortium partners.

Your profile:

• •Excellent Master’s degree in computer science, electrical engineering, computer engineering, or a related field.
• •Strong scientific curiosity and background in computer architecture, digital frontend design (RTL, e.g., SystemVerilog), or HW/SW co-design.
• •High motivation to conduct independent doctoral research and publish at premier international venues.
• •Strong interest or preliminary experience in machine learning hardware accelerators (NPUs), approximate computing, or fault-tolerant design.
• •Practical familiarity with standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, AMD/Xilinx Vivado, or comparable tools) and enthusiasm for physical silicon realization (tapeout).
• •Broad, interdisciplinary mindset capable of abstracting system constraints across the entire hardware/software stack.
• •Excellent interpersonal skills for collaborative research, along with fluency in English (written and oral).
• •Ability to take responsibility for advancing complex research and development topics.
• •Experience in industrial R&D, chip design, or EDA toolflows is an advantage.

[https://jobs.ruhr-uni-bochum.de/jobposting/20b694411a3e6de625f02c39d34c0b1864e721350?ref=AfA](https://jobs.ruhr-uni-bochum.de/jobposting/20b694411a3e6de625f02c39d34c0b1864e721350?ref=AfA)