Senior ASIC Design Engineer – Processor Subsystem

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking a Senior ASIC Design Engineer to join our processor subsystem team, focused on the configuration, integration, and verification planning of Arm processor IP and associated subsystem components for satellite IoT connectivity ASICs. This role sits at the intersection of RTL design and functional verification, requiring a strong grasp of processor subsystem architecture and hands-on experience bringing together complex IP in a cohesive, validated design. We are looking for dedicated self-starters who thrive in a fast-paced environment, can take ownership of complex technical challenges, and drive them through to completion with minimal oversight.