Senior CAD Semiconductor Engineer

Mission:

Define, deploy, and maintain EDA tool flows and CAD infrastructure supporting semiconductor design and verification activities across full SoC lifecycle.

Drive the evaluation, benchmarking, and integration of EDA tools (Cadence, Synopsys, Siemens EDA, Arteris) and associated flows to maximize productivity, reliability, and scalability.

Own the engineering infrastructure environment (compute, storage, licensing, CI/CD, automation) required for advanced chip design workloads.

Collaborate with design, verification, and physical implementation teams to ensure efficient, robust, and scalable tool usage .

Explore and integrate AI/ML-based tooling and workflows to improve engineering productivity (automation, debugging, optimization, knowledge extraction).

Ensure optimal trade-offs between performance, cost, scalability, and usability of the CAD environment.

Act as a key technical interface between internal engineering teams, management, and EDA vendors.

Provide regular reporting on tool performance, usage, and roadmap alignment .

Main responsibilities:

Define, deploy, and maintain EDA flows for digital, mixed-signal, and verification activities (simulation, synthesis, P&R, DFT, signoff).

Evaluate, benchmark, and qualify new EDA tools, releases, and methodologies before production deployment.

Design and operate EDA infrastructure environments , including:

• •Compute farms (Linux-based clusters for simulation and regression)
• •Storage systems (NFS, distributed storage, backup/DR)
• •License servers (FlexLM/Flexera)

Develop and maintain automation frameworks for:

• •Tool installation and configuration
• •Regression and CI/CD pipelines
• •Resource provisioning and monitoring

Implement and manage CI/CD pipelines (e.g., Jenkins, GitLab CI) for design and verification workflows.

Collaborate with engineering teams to:

• •Optimize tool usage and flows
• •Debug tool-related issues
• •Improve turnaround time and efficiency

Maintain strong interaction with EDA vendors (Cadence, Synopsys, Siemens):

• •Tool support, issue resolution, roadmap alignment
• •Licensing strategy and capacity planning

Define and enforce best practices and standards for CAD usage and tool flows.

Integrate AI-driven capabilities into engineering workflows, including:

• •LLM-assisted scripting and automation
• •AI-based log analysis, debug assistance, and workflow optimization
• •Hybrid cloud/on-prem AI infrastructure for sensitive data

Support security, compliance, and reliability requirements (e.g., ISO 27001 environments).

Technical skills:

EDA / CAD Flow Expertise:

Strong experience with full EDA flows:

• •Simulation, synthesis, place & route, verification, DFT flows
• •Tools from Cadence, Synopsys, Siemens EDA (Mentor Graphics)
• •Tool validation, qualification, and deployment

Strong experience with:

• •EDA licensing systems (FlexLM/Flexera)
• •Tool versioning, release management, and regression validation

Good understanding of:

• •RTL design, verification flows, and physical design constraints
• •Interaction between tools and silicon quality/productivity
• •Knowledge in ISO26262, DO-254 is a plus

Infrastructure & Automation:

Strong experience in:

• •Linux-based compute farms for EDA workloads
• •Distributed storage systems (NFS, parallel/distributed FS)
• •CI/CD systems (Jenkins, GitLab CI or equivalent)

Scripting and automation:

• •Python, Perl, Shell, TCL
• •Infrastructure-as-code and automation mindset

Experience with:

• •Monitoring and performance optimization
• •Backup, disaster recovery, high availability

AI / Modern Engineering Tooling:

Practical experience with:

• •AI/LLM-based tooling integration (e.g., Copilot, OpenAI, Gemini, Mistral)
• •Hybrid AI infrastructure (cloud + on-prem GPU environments)
• •Use cases such as:
• •Workflow automation
• •Debug assistance
• •Knowledge retrieval (RAG)
• •Engineering productivity optimization

Additional skills:

Object-oriented programming concepts

Familiarity with:

• •Version control systems (Git, SVN, etc.)
• •DevOps practices and toolchains

Requirements

Educational background:

Master’s degree (or equivalent) in Microelectronics, Electrical Engineering, or related field

Required experience:

• •8–15+ years in CAD / EDA / semiconductor infrastructure
• •Proven experience in EDA tool deployment and flow ownership
• •Strong exposure to semiconductor design environments