hirly

Altera

Senior Design Engineer

Regus, Madhapur

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at Altera first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included

Matched against 2.6M live jobs from 210,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude or ChatGPT and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending.

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority
Senior
Country
IN
Work mode
On-site / unstated
First seen by hirly
4 Nov 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Job Details:

Job Description:

Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.

Key Responsibilities:

1. Participate in design development tasks throughout the IP development flow.

2. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.

3. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

4. Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.

5. Involve in design example creation, simulation example creation, IP integration and release process.

6. Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Qualifications:

1. 8+ years' experience with bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.

2. Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis

3. Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script

4. Experience in FPGA design and programming is a plus.

5. Experience in RTL validation is a plus.

6. Ability to work with different teams, good communication and problem-solving skills.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Regus, Madhapur

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Original posting on Altera's site ↗

Listed on hirly, a job board. hirly is not the employer: Altera is hiring for this role.

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job