Capgemini Engineering

Senior Physical Design Engineer

Thessaloniki/Steliou Kazantzidi, Athinai, GR

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

Keywords matched to this posting
Fit score before you apply
Cover letter included

Matched against 2.6M live jobs from 190,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending. ChatGPT: manual setup today.

See how it works

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority: Senior
Country: GR
Work mode: On-site / unstated
First seen by hirly: 27 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Your role

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)
In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)
In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes
Be part of the overall Low Power solution development and implementation
Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from toplevel to block level)
Complete multiple design cycles of high complexity with little supervision

Desired qualifications/skills

8+ years in challenging RTL2GDSII work done on 10nm or below nodes with 500k –1million+ instances in designs
Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence
Good knowledge of synthesis flow, insertDFT scan/coverage and optimization
Excellent floorplan, power plan, CTS, place, route, and timing closure skills
Proficiency using Perl/TCL/Python scripting and Makefile
Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill
Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills
Experience with sign-off tape-out closure work
Any top level – floor planning, pin assignment – tape out activities is a plus