NVIDIA
Senior STA Engineer
Israel, Tel Aviv
hirly Pro
Get in front of the people hiring at NVIDIA
- Reach the hiring manager at NVIDIA on LinkedIn, from your own account
- hirly applies to this job for you, with unlimited applications
- A resume and cover letter written for this job, unlimited
- The hiring manager and recruiter at NVIDIA, with contact details
$49 a month · ₹1,999 for 30 days in India · cancel any time
Get past the screening software and onto a recruiter's desk
hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.
- Keywords matched to this posting
- Fit score before you apply
- Cover letter included
Matched against 2.8M live jobs from 210,000+ employers in 200+ countries.
Tailor my resume for this job →Apply from your AI assistant
Connect hirly to Claude or ChatGPT and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending.
Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.
hirly's read of this role
- Seniority
- Senior
- Country
- IL
- Work mode
- On-site / unstated
- First seen by hirly
- 2 Nov 2026
Derived automatically from the posting. Upload your resume above to see how the role scores against it.
the posting
NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels.
What you’ll be doing:
- Drive static timing analysis and timing closure for block and/or full-chip designs.
- Develop, review, and debug timing constraints, scenarios, and signoff checks.
- Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams.
- Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities.
- Review reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact.
- Improve timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python.
What we need to see:
- B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
- 5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation.
- Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure.
- Hands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalent.
- Experience debugging setup/hold violations, clocking issues, and ECO impacts.
- Solid scripting skills in Tcl plus familiarity with Perl or Python.
- Good communication skills and ability to work across design, CAD, and verification teams.
Ways to stand out from the crowd:
- Experience with advanced-node implementation and signoff.
- Knowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis.
- Experience improving timing methodology or developing reusable automation.
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided a reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. Please contact us to request accommodation.
Listed on hirly, a job board. hirly is not the employer: NVIDIA is hiring for this role.
Similar jobs
- Staff/ Principal Physical Design STA Engineer Asteralabs · Haifa District, IsraelFirst seen 6d ago
- Staff/ Principal Physical Design STA Engineer Asteralabs · Tel Aviv-Yafo, Tel Aviv District, IsraelFirst seen 58d ago
- Senior SoC STA EngineerInnophaseiot · San Diego, California, United StatesFirst seen 61d agoremote
- Lead STA EngineerBroadcom · IND-Pune EON Kharadi InfrastructureFirst seen 12d ago
- ASIC DFT STA EngineerCisco · San Jose, California, USFirst seen 16d ago
Browse similar roles
Want this one?
Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.
Tailor my resume for this job