Cadence

Software Architect

HSINCHU

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hirly's read of this role

Role family: Engineering
Seniority: Mid level
Country: TW
Work mode: On-site / unstated
First seen by hirly: 9 Nov 2026

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the posting

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title

EDA Architect Engineer – Debug, Analysis & FPGA Prototyping

Job Summary

We are seeking a highly experienced Frontend EDA Engineer to lead the development of design debug, analysis, and visualization tools for simulation and emulation solutions. The ideal candidate brings deep technical expertise in large‑scale RTL/netlist handling, performance optimization, and customer‑driven tool development, with a proven ability to collaborate closely with leading semiconductor and system companies.

Key Responsibilities

Frontend Debug & Analysis (Primary Focus)

Architect, design, and enhance frontend EDA tools for RTL/gate‑level debug, waveform analysis, and design visualization .
Drive performance, capacity, and usability improvements for large‑scale SoC designs.
Establish and maintain baseline performance metrics for interactive editing, debugging, and analysis flows.
Lead investigation and resolution of complex customer design issues involving RTL, netlists, timing, and simulation data.

Technical Leadership & Customer Engagement

Act as a technical owner for key frontend initiatives, from concept through deployment.
Partner closely with tier‑1 semiconductor and system customers to deliver high‑impact, production‑ready solutions.
Provide technical mentorship to senior and junior engineers across global development teams.
Translate customer requirements into clear technical roadmaps and executable plans.

Required Qualifications

MS in Computer Science, Electrical Engineering, or equivalent practical experience.
20+ years of experience in EDA tool development with strong emphasis on frontend debug/analysis .
Deep understanding of RTL, netlist, simulation, and verification flows .
Proven experience improving tool performance, scalability, and developer productivity .
Strong software engineering skills (C/C++, data structures, performance profiling, large‑codebase development).
Experience working directly with customers on complex design and tool‑flow challenges.

Preferred Qualifications

Hands‑on experience with Front end design debug platforms .
Background in FPGA‑based prototyping or emulation systems for SoC validation.
Experience leading cross‑site or multi‑disciplinary engineering teams .
Track record of delivering order‑of‑magnitude improvements in performance or productivity.
Patents or publications related to EDA, debug, or design productivity.

We’re doing work that matters. Help us solve what others can’t.

Original posting on Cadence's site ↗

Listed on hirly, a job board. hirly is not the employer: Cadence is hiring for this role.