Staff Engineer, Physical Design - Cores

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

About the Role --

• At SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Staff Physical Design Engineer (CPU Cores), you will own the physical implementation of critical, high-performance processor core blocks from RTL to GDSII. You will deliver high-frequency, power-efficient CPU designs on advanced and legacy process nodes.
• While your primary focus will be in physical design, we are looking for engineers capable of operating across design-abstraction layers. You will collaborate across architecture, RTL, and power teams. Leveraging a deep understanding of the processor pipeline and design goals, you will be instrumental in co-designing PPA (Power, Performance, Area) optimizations. This work directly enhances the frequency, area, and power-efficiency of our core IP.

Responsibilities - What you’ll do

Own Core Implementation: Drive the physical design implementation for high-frequency CPU core blocks and execution pipelines, managing synthesis, place & route, and signoff.

Engage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively collaborating with Architecture/RTL/Power for PPA co-optimisation. Understand the CPU microarchitecture to identify logic-depth bottlenecks early and suggest RTL pipelining strategies or structural changes.

Solve Core-Specific Challenges: Tackle physical bottlenecks unique to CPU cores, including timing closure, datapath placement, routing congestion, complex clock tree synthesis (CTS) for high-speed pipelines, and rigorous dynamic power optimization.

Aggressive PPA Optimization: Optimize block-level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex PPA trade-offs to meet target frequencies across various product lines.

Collaborate Cross-Functionally: Work closely with CPU architecture, RTL design, and Power teams to close design requirements and ensure efficient physical realization of the instruction set architecture.

Enhance Methodology: Support and improve physical design flows, automation scripts, and methodologies tailored specifically for high-frequency, complex core implementation.

Requirements - What you’ll bring

7+ years of hands-on experience in physical design implementation with a proven track record of block-level tape-outs involving high-speed digital logic like CPUs.

CPU/Datapath Expertise: Specific experience implementing complex control logic, execution units (ALUs, FPUs), or custom data-paths. Familiarity with the physical challenges of pushing high-frequency design limits.

Cross-Abstraction Awareness: A solid understanding of processor microarchitecture (e.g., instruction pre-fetch, execution units, data forwarding paths). You should be comfortable reading RTL to understand the design intent and collaborate effectively with front-end teams.

Strong Problem Solving: Proven ability to optimize for aggressive PPA targets using industry-standard physical design techniques, accompanied by a detail-oriented mindset and clear communication of results.

Tool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence implementation and sign-off tools.

Education: Bachelor’s or Master’s in Electrical or Computer Engineering.

Why join us?

Be part of the RISC-V movement and help define the future of computing architecture.

Work on industry-leading IP adopted by top customers and shipped in high volumes worldwide.

Collaborate with world-class engineers in a supportive, fast-paced, learning environment.

Enjoy a culture that values innovation, ownership, and technical excellence.

Our large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.