hirly

NXP

Verification Engineer II

Austin (Oakhill, Office)

See how you match this job — and similar ones. Free.

Upload your resume and hirly scores it against this role at NXP first, then against similar open jobs, and shows where you fit and why.

PDF or DOCX, up to 12MB. No sign-up to see your matches.

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

  • Keywords matched to this posting
  • Fit score before you apply
  • Cover letter included
Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending. ChatGPT: manual setup today.

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority
Mid level
Country
US
Work mode
On-site / unstated
First seen by hirly
27 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Job Title: Senior Verification Engineer

Location: Austin

Role Summary:

This position is within the MME MCU/MPU Digital IP team.

We develop best-in-class digital IPs for NXP’s automotive and advanced microcontroller businesses, delivering sensor and processing technologies that enable secure, connected vehicles today and autonomous vehicles of the future.

· Drive a “zero-defect” mindset across the verification team

· Provide technical leadership and guidance on complex verification challenges

· Mentor and grow a small team of engineers

Job Responsibility:

· Define and execute verification plans

· Develop and implement verification testbenches

· Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs

· Develop directed and constrained-random stimulus

· Analyze RTL, functional coverage, and assertion coverage results

· Define and develop functional coverage models

· Develop and maintain SystemVerilog assertions (SVA)

· Apply formal verification methodologies

· Demonstrate strong debugging skills, including failure reproduction and root-cause analysis

· Exhibit strong analytical and problem-solving skills; familiarity with major simulation and debug tools is a plus

Job Qualification:

· BSEE with 5+ years of semiconductor industry experience, or

· MSEE with 3+ years of experience, or

· PhD with 1+ years of experience

Technical Skills

· Knowledge of protocols such as DDR, PCIe, AMBA (CHI, ACE, AXI)

· Strong expertise in Verilog, SystemVerilog (VHDL is a plus)

· Experience with OVM/UVM and class-based verification methodologies

· Experience with formal verification methodologies

· Experience leveraging AI/LLM-based approaches to improve engineering efficiency

· Test pattern debugging and validation on simulation and automated test environments

· Scripting in Python, Perl, and UNIX/Linux

· Familiarity with functional and code coverage methodologies

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

#LI-6692

Original posting on NXP's site ↗

Listed on hirly, a job board. hirly is not the employer: NXP is hiring for this role.

Browse similar roles

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job