Ambarella

VLSI Physical Design / APR Engineer

Taiwan Hsinchu

hirly Pro

Get in front of the people hiring at Ambarella

Reach the hiring manager at Ambarella on LinkedIn, from your own account
hirly applies to this job for you, with unlimited applications
A resume and cover letter written for this job, unlimited
The hiring manager and recruiter at Ambarella, with contact details

Get Pro for this job →

$49 a month · ₹1,999 for 30 days in India · cancel any time

Get past the screening software and onto a recruiter's desk

hirly rewrites your resume for this job — matching the keywords and skills in the posting, moving your most relevant experience to the top, and writing a cover letter to fit. About 30 seconds.

Keywords matched to this posting
Fit score before you apply
Cover letter included

Matched against 3M live jobs from 220,000+ employers in 200+ countries.

Tailor my resume for this job →

Apply from your AI assistant

Connect hirly to Claude or ChatGPT and ask it to apply to this job. hirly tailors your resume, fills the employer’s form and asks before sending.

See how it works

Some employer sites stop an application at a CAPTCHA or sign-in and hand it back with a link. Applying needs a paid plan. Works with any assistant that supports MCP.

hirly's read of this role

Seniority: Mid level
Country: TW
Work mode: On-site / unstated
First seen by hirly: 1 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good.

Key responsibilities:

1. Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII).

2. Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications.

3. Work closely with front-end design, DFT, and package teams to ensure design closure.

4. Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM).

5. Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues.

6. Create and maintain physical design automation Tcl scripts, and flows development for design implementation.

7. Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.

Job Requirements:

1. Minimum Master degree majoring in EE/CE/CS related fields.
2. At least 2 years ~ 7 years of experiences in VLSI field for designer and manager positions, respectively.
3. Experience in tapeout with multi-million gates count SOC design, 10/7/5/3nm design experience is a plus.
4. Solid skill sets of one of Cadence/Synopsys/Mentor EDA tools.
5. Experience in design methodology, flow deployment/refinement and problem solving skill.
6. Familiar with Perl/TCL scripting is a plus
7. Proficiency in speaking and writing English is a plus.
8. Good communication skill, team spirit, initiative, innovative and fast learning.

Original posting on Ambarella's site ↗

Listed on hirly, a job board. hirly is not the employer: Ambarella is hiring for this role.

Want this one?

Upload your resume and hirly rewrites it for this job and writes the cover letter — in about thirty seconds, before you sign up.

Tailor my resume for this job