ASIC Design and Verification Intern, SOC - 2027

The NVIDIA SOC group is looking for ASIC Design and Verification Interns to join the SysASIC and Clock teams. In this position, you will participate in the design and verification of complex reset/fuse/ism/sysctrl/boot and clock-related logic for latest NVIDIA products. You will work closely with global teams across Architecture, ASIC Design, Verification, DFT, Physical Design, Firmware, and Software.

What You’ll Be Doing:

Participate in RTL design and verification of SysASIC and clock-related IPs

Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions.

Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification.

Collaborate with cross-functional teams to improve design quality, verification coverage, and development efficiency.

Develop scripts, automation tools and AI agent to improve design and verification flows.

What We Need to See:

Pursuing a BS/MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Understanding of digital logic design and front-end ASIC development flow, including RTL design, simulation, synthesis, STA, lint, and CDC/RDC.

Familiarity with clocking concepts, such as clock gating, clock-domain crossing, reset synchronization, PLLs, and timing fundamentals.

Proficiency in Verilog and/or SystemVerilog; knowledge of UVM, SVA, or functional coverage is a plus.

Familiarity with formal verification concepts and tools, including property specification, assertion-based verification (SVA), equivalence checking, or formal property verification

Experience with Python, Perl, Tcl, shell scripting, C, or C++ is preferred.

Familiarity with Linux development environments and common EDA tools.

Strong analytical and debugging skills, attention to detail, and willingness to learn.

Good English communication skills and the ability to work effectively in a global team.

Ways to Stand Out from the Crowd:

Experience through coursework, projects, or internships in RTL design, ASIC verification, Formal Verification, SOC integration, clocking, low-power design, or FPGA development.

Hands-on experience with UVM, assertions, functional coverage, CDC/RDC verification, STA, or gate-level simulation.

Experience developing automation tools or applying AI-assisted methods to design and verification workflows.