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Neuralink

Digital Verification Engineer

South San Francisco, California, United States

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hirly's read of this role

Seniority
Mid level
Stated salary
$131,000 – $243,000 per year
Country
US
Work mode
On-site / unstated
First seen by hirly
1 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Job Description & Responsibilities:

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP) . We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Required qualifications :

Minimum 3 years of experience in digital ASIC verification.

Excellence in SystemVerilog.

Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell

Experience with code coverage and regression setup.

Bachelor's degree in a technical field OR equivalent experience.

Preferred qualifications :

Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.

Experience on building test benches, testing, and debugging for a complex system-on-chip.

Experience in formal verification.

Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.

Experience with IEEE-1801 (UPF) based design simulation flows

Experience with low power gate level simulations

Exposure with low power formal verification flows

Strong hands-on experience in verification methodologies such as UVM

Knowledge of ARM/RISC-V processor, AMBA bus

Knowledge of power aware verification

Experience with FPGA/emulation

Experience with lab system bring up, writing diagnostic, and lab debugging

Expected Compensation:

The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range:

$131,000 — $243,000 USD

What We Offer:

Full-time employees are eligible for the following benefits listed below.

An opportunity to change the world and work with some of the smartest and most talented experts from different fields

Growth potential; we rapidly advance team members who have an outsized impact

Excellent medical, dental, and vision insurance through a PPO plan

Paid holidays

Commuter benefits

Meals provided

Equity (RSUs) *Temporary Employees & Interns excluded

401(k) plan *Interns initially excluded until they work 1,000 hours

Parental leave *Temporary Employees & Interns excluded

Flexible time off *Temporary Employees & Interns excluded

Original posting on Neuralink's site ↗

Listed on hirly, a job board. hirly is not the employer: Neuralink is hiring for this role.

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