FPGA IP Solution Design & Verification Engineer

Job Details:

Job Description:

As an FPGA IP Solution Design Engineer at Altera, you will be responsible for designing, developing, and verifying high-quality intellectual property (IP) solutions for Altera's leading-edge FPGA devices. This role involves working across the full IP lifecycle, from architectural definition to customer support.

Key Responsibilities

• •Develop FPGA logic designs, RTL code, and simulation environments for functional units, IP blocks, subsystems, and reusable libraries.
• •Participate in the definition of block architecture and microarchitecture, translating system requirements into implementable FPGA designs.
• •Create prototypes, behavioral and RTL models, and system specifications to support feature development and validation.
• •Prepare logic diagrams and implement RTL that meets system design and test specifications.
• •Develop and deliver software and hardware models that support device-level bring-up, including user-visible functionality, timing, and power behavior.
• •Apply RTL implementation techniques to achieve required power, performance, and area targets; partner with physical implementation teams to qualify designs.
• •Design, implement, and maintain FPGA verification environments, testbenches, simulations, and regression tests.
• •Review verification plans and implementations to ensure design features, corner cases, and requirements are verified correctly.
• •Analyze failing RTL tests, identify root causes, and implement corrective actions to ensure feature correctness and robust operation.
• •Integrate and debug Ethernet MAC, PCS/PMA, and related protocol-stack functionality in FPGA-based platforms.
• •Bring up and validate FPGA designs on hardware, including high-speed interfaces, Gigabit transceivers, clocks, resets, and board-level connectivity.
• •Use Quartus design, compilation, timing analysis, programming, and debug flows to build, optimize, and troubleshoot FPGA images.
• •Perform platform-level debug using FPGA observability tools and lab equipment such as oscilloscopes, logic analyzers, protocol analyzers, signal generators, power supplies, and related test equipment.
• •Investigate design, integration, timing, signal-integrity, and system-level issues; drive issues to resolution in collaboration with cross-functional engineering teams.
• •Document architectures, design decisions, verification results, bring-up procedures, debug findings, and validation status.

Qualifications:

• •Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• •2+ years of experience in digital IC design, with a strong focus on FPGA design and development.
• •Proficiency in RTL design using Verilog or SystemVerilog.
• •Solid understanding of FPGA architectures and design flows (e.g., Altera Quartus Prime, Xilinx Vivado).
• •Experience with verification methodologies (e.g., UVM, SystemVerilog Assertions) and simulation tools.
• •Familiarity with industry standard protocols (e.g., PCIe, Ethernet, DDR, AXI).
• •Experience with scripting languages (e.g., Python, Perl, Tcl).
• •Strong analytical and problem-solving skills with attention to detail.
• •Excellent written and verbal communication skills.
• •Ability to work independently and collaboratively in a fast-paced environment.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.