Astera Labs
Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms
San Jose, California, United States
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hirly's read of this role
- Seniority
- Director
- Country
- US
- Work mode
- On-site / unstated
- First seen by hirly
- 10 Sept 2026
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the posting
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
About Astera Labs
Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume — and as OEM customers increasingly adopt Astera Labs silicon into their own designs — we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success.
About the Role
We are hiring a Senior Director, Hardware Design Engineering to lead and scale Astera Labs' hardware design engineering organization across Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms (SVB/EVB), rack-scale products, and OEM/customer design enablement. This is a senior leadership role with full ownership of the hardware design function — encompassing electrical/PCB design, mechanical engineering, hardware validation, lab infrastructure, and customer hardware engineering support.
You will build and lead a world-class, multidisciplinary engineering organization that takes products from concept through design, validation, qualification, and production release — while simultaneously enabling OEM customers and design partners to successfully integrate Astera Labs silicon into their own products. Your teams will own the complete hardware realization of Astera Labs' connectivity products and serve as the technical bridge between Astera Labs' silicon capabilities and the broader ecosystem of customers building next-generation AI infrastructure.
You will be a key member of the engineering leadership team, driving technology roadmaps, making critical technical and business trade-off decisions, and partnering closely with silicon, firmware, signal integrity, NPI, manufacturing, quality, product management, sales, and customer-facing teams. You'll also be responsible for attracting, developing, and retaining top engineering talent as Astera Labs scales through hyper-growth.
Key Responsibilities
Engineering Leadership & Organization Building
Lead and scale Astera Labs' hardware design engineering organization, encompassing:
Electrical/PCB Hardware Design Engineering — schematic capture, high-speed PCB/flex/substrate layout, power delivery, component engineering for cable modules through rack-scale systems
Mechanical Engineering — connector design, housing/enclosure design, thermal management, cable strain relief, chassis/sheet metal, form factor compliance, tolerance analysis
Hardware Validation Engineering — product-level electrical, mechanical, environmental, and reliability qualification and validation across all product lines
Lab Engineering & Infrastructure — test lab buildout, capital equipment strategy, measurement capability, and lab operations
Customer Hardware Engineering & OEM Enablement — reference design support, design reviews, integration guidance, and hands-on technical engagement with OEM customers adopting Astera Labs silicon
Build, mentor, and lead a team of engineering managers and senior individual contributors across all hardware design disciplines
Define organizational structure, hiring plans, career development frameworks, and technical competency models as the team scales
Foster a culture of engineering excellence, rigorous design practices, cross-functional collaboration, and customer-centric technical support
Represent the hardware design engineering function in executive reviews, board updates, and strategic planning sessions
Technology Roadmap & Strategic Planning
Define and manage the hardware technology roadmap for AEC, SCM, Silicon Evaluation Platforms, and rack-scale products — aligned with silicon roadmaps, customer requirements, market trends, and competitive dynamics
Drive technology strategy decisions across interconnect architectures, PCB/substrate technologies, connector platforms, cable constructions, thermal solutions, chassis architectures, and form factors
Identify and invest in next-generation hardware technologies (e.g., 224G/lane substrates, advanced thermal materials, novel connector interfaces, miniaturized form factors, liquid cooling integration) that maintain Astera Labs' competitive differentiation
Partner with Product Management and Business Development to translate customer needs, market requirements, and standards evolution into engineering development priorities
Align hardware design roadmap with silicon tape-out schedules, firmware development timelines, manufacturing readiness milestones, and OEM customer design-in timelines
Incorporate customer and OEM feedback into technology roadmap decisions — ensuring reference designs, evaluation platforms, and design collateral evolve to meet ecosystem needs
Product Development & Execution
Drive R&D and new product development for the full range of hardware products — from cable-scale modules to rack-scale systems:
Active Electrical Cables (AEC) — high-speed active cable products with integrated retimer silicon
Smart Cable Modules (SCM) — advanced cable modules with intelligent management and diagnostic capabilities
Silicon Evaluation Platforms (SVB/EVB) — evaluation boards and system validation platforms that enable silicon bring-up, characterization, and customer evaluation
Rack-Scale Products — AI chassis-class systems, switch trays, CEM cards, and associated system-level hardware
Reference Designs & Customer Enablement Hardware — reference schematics, layout guidelines, and demonstration platforms that accelerate OEM adoption of Astera Labs silicon
Oversee products through the full design lifecycle — from architecture definition, schematic/layout design, mechanical design, prototype build, validation, qualification, to production release
Ensure rigorous design review processes at each stage (architecture, schematic, layout, mechanical, pre-production) with clear entry/exit criteria and cross-functional participation
Make critical technical trade-off decisions that balance performance, cost, manufacturability, schedule, and risk across the product portfolio
Drive schedule discipline and engineering milestone execution — ensuring products hit market windows aligned with customer platform cycles and silicon availability
Electrical & PCB Design
Oversee high-speed PCB, flex circuit, and substrate design across the full product portfolio:
AEC/SCM: Retimer integration on flex/substrate, high-speed routing, power delivery, dense component placement in constrained cable module form factors
Silicon Evaluation Platforms: Complex multi-layer PCBs for silicon bring-up, high-speed channel characterization, and reference design generation
Rack-Scale Products: Backplane/midplane design, switch tray PCBs, CEM card layouts, chassis power distribution, and high-density connector interfaces
Reference Designs: Production-quality schematics and layouts that serve as starting points for OEM customers integrating Astera Labs silicon
Ensure designs meet signal integr
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