Infineon Technologies Austria AG

Ingenieur/in - Elektrotechnik

Villach-Auen, Kaernten, Austria

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hirly's read of this role

Role family: Engineering
Seniority: Mid level
Country: AT
Work mode: On-site / unstated
First seen by hirly: 16 Oct 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Job id: HRC1744552

Job familyResearch & DevelopmentDuration of employmentBefristetArt des ArbeitsplatzeshybridEinsteigen alsBerufserfahrene*r

#WeAreIn for jobs that impact everyone's life.

What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Engineer Mixed Signal Layout in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?

Your role

Key responsibilities in your new role

Full Custom Layout: Execute full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components

Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends

Physical Verification: Run and debug full-chip physical verifications, including DRC, LVS, ERC, and antenna rule checks

Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity

Top-Level Integration: Perform floor planning, pad-ring assembly, and final chip integration, considering ESD, latch-up, and electromigration (EM) guidelines

Leadership & Mentorship: Provide technical leadership during project execution and mentor junior layout engineers within the team

Your profile

Qualifications and skills to help you succeed

A bachelor's or master's degree in electrical engineering or a comparable field

Ideally 5+ years of hands-on experience in CMOS and FinFET semiconductor technologies

High proficiency with industry-standard EDA tools (Cadence Virtuoso, Siemens Calibre, etc.)

Excellent analytical skills to independently debug complex layout and physical verification issues

Excellent communication skills to bridge technical gaps across global, multidisciplinary engineering teams

The ability to guide, motivate, and coordinate small layout teams during project execution, and to collaborate closely with ADC Design Engineers

Fluent in English

This position is initially limited to a period of 2 years. We offer competitive salaries and additional benefits based on your performance, experience and qualifications. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group F-G (https://www.feei.at/leistungen/informations-service/mindestlohne-und-gehalter). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

Apply to this position online by following the URL and entering the Job ID in our job search.

https://www.infineon.com/jobs

Original posting on Infineon Technologies Austria AG's site ↗

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