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Astera Labs

Principal Hardware Validation Engineer

San Jose, California, United States

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hirly's read of this role

Seniority
Lead / management
Country
US
Work mode
On-site / unstated
First seen by hirly
10 Sept 2026

Derived automatically from the posting. Upload your resume above to see how the role scores against it.

the posting

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

As a Principal Hardware Validation Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others.

Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products.

Key Responsibilities

Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.

Develop comprehensive hardware electrical validation plans using correct test methods and processes.

Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.

Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.

Rework components on the PCBAs to unblock debugging activities.

Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.

Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.

Support the new designs using knowledge of existing products to de-risk new features and requirements.

Self-informed of new industry test standards and equipment to introduce modern testing methodologies.

Specify test equipment, develop test fixtures, help improve hardware lab functions.

Required Skills

Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug

Bachelor degree in EE with 3+ years of experience in hardware test or design

Expert understanding of design and test for power regulators, PDNs, Bode, clock generators

Ability to produce test description from a schematic design, and execute and document results

Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM

Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.

Automating lab equipment to optimize test processes, Python preferred

Preferred Skills

Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.

EMI/EMC compliance

Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.

PLM, Arena or equivalent

Understanding of the ASIC/silicon product development process

The base salary range is $185,000 USD - $240,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Original posting on Astera Labs's site ↗

Listed on hirly, a job board. hirly is not the employer: Astera Labs is hiring for this role.

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